How can I calibrate a retail digital clock that uses a 32.768 kHz crystal?

Question

SOLVED: SEE BELOW ORIGINAL QUESTION FOR IMPLEMENTED SOLUTION

I have two Sony Dream Machine clocks. They are different models; one seems to use the mains frequency and is keeping its time precisely, while the other (model: ICF-C414) seems to be using the onboard crystal to keep the time. This leads to running too fast 1 second per day (30 seconds per month and 6 minutes per year).

If possible, I'd like to modify this clock to be more accurate, since the drift is known (1 second per day). Is there anything I can do to reduce this drift?

I considered just buying a new crystal and seeing if that has better accuracy, but I can't find any 32.768 kHz crystal with better than 20 ppm accuracy.

Here are the circuit board pictures:

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Thank you all for your help, this wouldnt be possible without your education.

Problem: Clock gains ~1 second every ~24 hours

Attempt1: Attempt 1 was to simply change the crystal to a high quality 5ppm CITIZEN crystal (CFS-20632768HZFB). This did not yield a better result. Clock was still gaining ~1 second every ~24 hours.

Attempt2: Check continuity to make sure correct capacitor is used from one of the legs of the crystal to one of the sides of the capacitor C204. After confirming I attached 10pF capacitor (FG28C0G2A100DNT06) directly to C204. So far 48 hours later there appears to be no gain/loss. I will observe over the course of a few weeks to determine if there is a slow gain/loss and adjust accordingly by going either to 11pF (10pF + 1pF caps) or 9pF (6pF + 3pF caps).

Attempt 3: With 10pF capacitor the clock lost 1 second after 4 days. Means loss of 0.25seconds every 24 hours. This is 1.25 second swing per 24 hours (was too fast now slow) from before any capacitors were attached. If capacitance (pF) influence on the crystal is linear this means 1pF slows the clock down 0.125 seconds per day. Meaning that by lowering down to 8pF capacitor I should achieve 0.25 faster clock speed, which would bring it closer to 0. Replaced 10pF capacitor with 8pF (6pF + 2pF). Will report on results.

Attempt 4: With 8pF cap the clock lost 1 second per ~6 days. This means each 1pF does not influence the clock linearly. Removed the 2pF (from 6pF + 2pF) and will test it at 6pF. Will update with results. It seems like I am getting close. Even as it is 8pF improvement was ~1 minute off per year versus unmodified ~6 minutes off per year. Hoping to achieve ~1 sec per month/~12 per year or better, but 1pF increments may not allow for this. Will get as close as I can and report here.

Attempt 5: After much experimenting I found the balance, it is somewhere between 6pF and 7pF. To be more granular Id have to order sub 1pF capacitors. Currently with 7pF (6pF + 1pF) I achieved 1 second loss (slow) every 2 weeks or so. Which is sub 30 second drift per year. I am more than happy with the result. If I come across some sub 1pF caps Ill attempt something like 6.5pF (6pF + 0.5pF) to see if I can nail it even closer. Thanks all for your help!

Answer 1

Here is an 5 ppm 32768 Hz crystal in stock at Digi-Key.

Here are 20, 10 ppm 32768 kHz crystals in stock at Digi-Key.

It is difficult to match the long-term accuracy of power line frequency. It is continually adjusted to maintain network grid performance. Crystals outperform the power line short term.

^{simulate this circuit – Schematic created using CircuitLab}

C203, C204, and R214 are from the image that you provided. Within the crystal equivalent diagram, the components with subscript "m" are the motional values. Co is the shunt capacitance between the pins.

The load capacitance \$C_{L}\$ required for the crystal to function is:$$C_{L}=C_{0}+\frac{C_{203}C_{204}}{C_{203}+C_{204}}$$

The datasheet for the linked 5 ppm capacitor has \$C_{L}=12.5\ pF\$ and \$C_{0}=1.2\ pF\$, so:$$\frac{C_{203}C_{204}}{C_{203}+C_{204}}=11.3\ pF$$. If they are equal then:$$C_{203}=C_{204}=22.6\ pF$$ The stray capacitance are probably 1 to 2 pF. Cin is harder to estimate, perhaps 2 to 5 pF. Perhaps others here can provide better estimates. \$C_{203}\$ and \$C_{204}\$ must be reduced to compensate.

The drive level for the 5 ppm device must be \$<1\ \mu W\$ for others \$<0.5\ \mu W\$. Typically they operate at 20% of the maximum. For series resonance, the power can be calculated using the motional resistance and the voltage drop across the crystal.

For the 5 ppm crystal the voltage drop should be less than 187 mV_RMS. Probably closer to 50 mV. Because a scope's capacitance will load the crystal, I would increase R214 to the point where the oscillations stop. Then decrease until they start again. Then a further reduction of 10% to 20% will allow operation over temperature.

What are the chances that the new crystal will just work? Try it and see. But making sure the capacitance is right will put it at the right frequency.

To trim the frequency either one or both of \$C_{203}\$ and \$C_{204}\$can be adjusted to get the frequency.

Use NP0 ceramic capacitors. X5R, X7R and all other ceramics are severely voltage and temperature dependent.

Answer 2

First, refer to this post for details of (we hope) the underlying oscillator schematic. You'll probably just see the crystal and the caps, with traces going into a chip.

• Verify that you've found the crystal and its load caps.
• It looks like the capacitors are surface-mount, so they won't be marked and you'll need some good soldering skills. Don't trash the board.
  • (that is a weird board layout, BTW -- "value design" rules, I guess).
• If the clock is running fast, adjust one cap value up slightly -- I'm talking like 1pF at a time here, so be patient. If that doesn't overshoot, but doesn't get you where you want, adjust the other one up by 1pf. Repeat as necessary until things work.
• If the clock is running slow, adjust one cap value down slightly, i.e., do the reverse of the step above.

Chances are that to start from a known point you'll have to replace the caps on the board anyway. I'd be strongly tempted to replace one or both caps with variable capacitors whose ranges center on 12pF, then tweak them. I'd also be strongly tempted to use 10pF fixed caps in parallel with variable caps whose range is centered on 2pF -- this will mean that you'll get less change in frequency for the amount you tweak the cap, which will, in turn, make your life easier.

Before you even launch on this quest, though, you may want to take the clock and put it in a space with a markedly different temperature than what you've been testing it -- chances are that if they didn't care about one second per day when they were designing it, they also didn't care about variation of frequency with temperature. If that's the case, then you could get lost in a very deep rabbit-hole trying to get the thing adjusted and stable over temperature.

Answer 3

Since the clock is running fast, you could try increasing the capacitance on the crystal by using a "gimmick", which is a capacitor made by two insulated wires twisted together. Magnet wire would probably work best because of the thin insulation.

The Wikipedia article says capacitance is around 1 pF/inch (0.4 pF/cm). You might try a couple of inches (5 cm) to see if it runs slow, and then just snip off pieces until it is a close as possible.

Answer 4

You can add a TCXO such as Maxim's DS32kHz to the board if you like.

1. Glue the chip down, preferably on a ground pour (dead bug style- legs in the air).

2. Remove R214 (0Ω resistor).

3. There are four connections required to the chip. Attach (using AWG30 Kynar wire-wrap wire or magnet wire) GND and Vcc connected together (to pin 11 on IC101), Vbat (to pin 14 on IC101), and 32kHz (to pin 13 on IC101, where one side of R214 went).

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Or just muck with either one the caps (C203/C204). They're 22pF and you can get a trimcap and a few values of smt capacitor to get more values. I'd aim for 10pF +/-5pF more than the 22pF as just an educated guess based on estimated pullability of a random 32kHz tuning fork crystal and your 'running fast' number. So just connect the trimcap in parallel with one of the existing caps.

Answer 5

Watch crystals are rarely more accurate than the 20 ppm you say. So replacing the crystal likely makes little difference. It might tick at wrong rate too, in that circuit, because you don't know the load capacitance rating of the crystal to replace it with a crystal that has a matching load capacitance rating.

But crystals are tuned by adjusting the load capacitance. You could replace crystal load capacitors with slightly smaller or higher capacitors, depending on if you want to slow it down or speed it up.

One of the capacitors can be replaced with an adjustable capacitor.

It can be difficult to determine the exact frequency accurately with home equipment, but measuring the drift over time as you have done so far is a good method.

Answer 6

If you really want it to be in time with a powerline clock, you could always tick off the powerline. Fortunately you have a transformer, so isolated zero-crossing detection is easy (clipping diodes and a large resistor to the high side of the secondary: with old microcontrollers people used to use the internal protection diodes); then you'd need some kind of PLL, either in software on a microcontroller or in hardware (fortunately this is easy as 32.768 is chosen to divide down nicely!).

Whilst I suspect this is more than you want to get involved in, are you sure it's not already possible? I do wonder if @Harper's comment isn't correct. If you compare the board from the powerline-disciplined clock, can you find the powerline circuitry? Is it present? If it isn't and it feeds a pin on that MCU as I suspect it does, what happens if you feed that pin on the non-working clock? There's a chance it's not disabled in software, particularly if the powerline clock also has a crystal present---it would be sensible to have put failover in there.

If you don't go for powerline disciplining, the two clocks are going to get out (even if you go for something better like GPS disciplining, they'll be out most of the time by average). But you can probably trim for better than 1/s day as per the other answers.