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I am working on a design of a PFD for a PLL. I came across an issue of dead zone which requires a minimum time for the switches to be on so the charge pump works the way we want (image 1.)

The solution for this is that we add an additional delay (image 2), so that the charge pump works in the required way.

I have two doubts here:

  1. How can we decide the minimum switch time?
  2. What if the minimum delay time causes an issue with the blind zone, which means that a missing pulse in the reference signal due to a reset signal? (See image 3.)

Added:

I am trying to conceptualize the idea of dead zone and blind zone. Here, usually in PFD we face the issue of dead zone, where the up or down pulse is very narrow such that the switches can't be on for small on time. We tried to extend it by adding delay before the output is given to the reset of normal DFF based PFD.

How can the dead zone problem be resolved using extending the time delay? If it happens, what will happen to the worst case scenario ie the third image, where we miss a reference pulse?

image 1

image 2

image 3

PFD with charge pump

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  • \$\begingroup\$ I have read this the third time now and still don't understand the context of the problem. Is there a charge pump driven by a PLL? Why? Can you provide a schematic? \$\endgroup\$
    – Jens
    Sep 14, 2022 at 18:00
  • \$\begingroup\$ I am trying to conceptualize the idea of dead zone and blind zone. Here, usually in PFD we face the issue of dead zone, where the up or down pulse is very narrow such that the switches cant be on for small on time. So, we try to extended it by adding delay before the output is given to the reset of normal DFF based PFD. My question is that , how the dead zone problem can be resolved using extending the time delay. If it happens, what will happen to the worst case scenario ie the third image, where we miss a reference pulse @Jens \$\endgroup\$ Sep 15, 2022 at 6:45
  • \$\begingroup\$ @Jens I am adding the schematic of Charge pump as fourth figure \$\endgroup\$ Sep 15, 2022 at 6:46
  • \$\begingroup\$ Unhelpful comment :-) - Do what it takes. There is always some way of achieving what you want. Here either your charge pump drive or your signal on time are most important. If you cannot find a compromise that suits both then favour the most important and find another way to do the other. In this case a charge pump can quite easily and cheaply be driven by a separate switch. This is inconvenient but no big deal if it has to be done. \$\endgroup\$
    – Russell McMahon
    Sep 15, 2022 at 12:10
  • \$\begingroup\$ @Jens Does negative_feedback's clarifications now make the question clear enough. If so, some related action may be in order. If not, further comment welcome. \$\endgroup\$
    – Russell McMahon
    Sep 17, 2022 at 11:29

1 Answer 1

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PSD dead zone is, or is not, a problem in PLLs, depending on whether you are implementing an integer or a fractional-N design.

In an integer design, you only have to provide enough delay time so that the logic works correctly. As the PSD switches at the same point on every cycle, there is no additional issue.

In a fractional-N design, the dead zone introduces a fatal non-linearity, that down-converts the high frequency noise produced by the fractional N algorithm down into the baseband. Sometimes the divided pulse arrives ahead of the reference, sometimes behind. The algorithm assumes that equal times == equal weights. The PSD non-linearity breaks this assumption. Any attempt to use more delay to reduce the problem only ameliorates it slightly, it does not solve it.

The answer for frac-N systems is to lock with divided and reference pulses 180 degrees out of phase. That way, the pulses are always in the same order, and spaced in time from each other. This is how the highest quality frac-N systems are implemented, for instance MI/IFR/Aeroflex 203x, 204x, 2023/4/5, 3010.

Here is a PSD as shown in patent US4851784 (long since expired so no IP issues).

enter image description here

This looks similar to the 'three-state' PSD you have shown in the question, but there is an extra stage in the middle, to make it into a 'four-state' PSD. In fact, there is a whole family of N-state PSDs that can be built, as described in that patent. PSDs with an odd number of states lock in phase. PSDs with an even number of states lock 180 degrees out of phase. Even state PSDs are required for proper implementation of fractional-N synthesisers.

Should you look up that patent, then yes, it's the same Neil.

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  • \$\begingroup\$ I will check on this @Neil_UK \$\endgroup\$ Sep 23, 2022 at 7:00

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