0
\$\begingroup\$

I would like to build a nixie tube clock with a unique idea. The idea is that the clock queries the accurate time (it respects the DST too) from my home server. So the clock does not require any button or something like that if my home server is available. Even quartz can be less accurate.

A 3.3 V ATmega8A microcontroller drives a high-voltage shift register (HV5622) with a 12 V power supply via SPI.

I would like to solve this problem in the simplest way possible without having any invert logic between the two sites.

Will the following solution work? The MCU is on the left side, the shift register is on the right side.

enter image description here

If not, what would be a good solution?

The full schematic is available here on github.

Note: I know the POL pin of the shift register should be grounded.

\$\endgroup\$
4
  • \$\begingroup\$ Can you use the same circuit as used for LE and BL and generate inverted logic signals in the MCU (different clock phase and polarity)? The 100 kohm is a bit high for SPI signals, 10 kohm sounds better. \$\endgroup\$
    – Jens
    Sep 14, 2022 at 20:48
  • 2
    \$\begingroup\$ No, a source-follower (common-drain) configuration of transistors will not work. For level translation, you need to use a configuration that has voltage gain. Common-source is the simplest, but inverts the logic levels. Common-gate does not invert, and is often seen in bi-directional signalling applications. \$\endgroup\$
    – Dave Tweed
    Sep 14, 2022 at 21:57
  • \$\begingroup\$ What frequency will the SPI running at? \$\endgroup\$ Sep 15, 2022 at 6:29
  • \$\begingroup\$ Thank you for all of your comments. They are valuable for me. Probably, I will go with the same circuit as the LE and BL pins have with 10 kohm resistor. There is an option in MCU to change the polarity of clock. And yes, the data needs to be inverted within MCU. The frequency of SPI is 55 kHz. The lowest available. \$\endgroup\$ Sep 15, 2022 at 19:44

1 Answer 1

0
\$\begingroup\$

A two BJT transistor solution is shown below. Select R2 and R5 to provide a collector current of say 10mA to 30mA. The 3904s can handle more if the SPI speed requires it. Select R1 so that Q1 is just in saturation so that turn-off is quicker. The voltage divider (R3 and R4) serves two functions. First when Q1 is on, then the divider makes sure that Q2 is off. When Q1 is off, then R2,R3, and R4 serve to place Q2 just into saturation. Operating Q1 on 3.3V and Q2 on 12V provides good isolation between the voltage domains.

schematic

simulate this circuit – Schematic created using CircuitLab

A common gate solution, suggested by Dave Tweed in the comment, is shown below. The gate threshold must be such that 3.3V exceeds the Miller plateau voltage. When Q1 turns off the rising drain voltage edge is coupled through CDS to the source requiring D1 to divert the current to the decoupling capacitor C1. Choose R3 to limit the current into the microcontroller so not to exceed the rating for the pin.

schematic

simulate this circuit

\$\endgroup\$
1
  • \$\begingroup\$ Thanks for the detailed answer. It was a long time ago, when I studied electronics :). \$\endgroup\$ Sep 15, 2022 at 19:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.