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I am connecting an NAND logic gate output to a Pchannel mosfet gate and intending under normal conditions to sink current into the NAND output. But there are two scenarios about this setup which are somewhat troubling.

  1. There are many times when the source of the P-MOSFET is non zero but the Vcc of the Nand gate is zero. Making me wonder what will the voltage on the MOSFET's gate be during this time, and will it damage the NAND's logic gate output?

  2. What would happen if the source and drain of the MOSFET were approximately 12V but my logic gate only outputs 0-5V? can I still prevent the MOSFET from conducting?

schematic

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2 Answers 2

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There are many times when the source of the P-MOSFET is non zero but the Vcc of the Nand gate is zero. Making me wonder what will the voltage on the MOSFET's gate be during this time, and will it damage the NAND's logic gate output?

The gate will be one diode drop above GND or less. Possibly at GND, which means the PMOS will be ON.

What would happen if the source and drain of the MOSFET were approximately 12V but my logic gate only outputs 0-5V? can I still prevent the MOSFET from conducting

No, you cannot reliably prevent the MOSFET from conducting in this scenario.

What you might want to do is add a pullup from the gate to source of the PMOS, then use an NMOS to turn the PMOS on and off. The NMOS gate in this scenario would have a pulldown, and the gate would be driven by your logic (you might have to invert it compared to what you are doing now).

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  • \$\begingroup\$ I am not disagreeing but why would the gate be one diode drop above ground? \$\endgroup\$
    – Feynman137
    Commented Sep 17, 2022 at 3:17
  • \$\begingroup\$ @Feynman137 It probably wouldn't be. But if there was some small leakage current, it might be possible for it to be that high. It is very hard to predict the exact voltage of a mosfet gate connected to a de-powered output of a digital IC. Most likely the gate would simply be at ground potential (or very close). \$\endgroup\$
    – user57037
    Commented Sep 17, 2022 at 3:21
  • \$\begingroup\$ Inside the logic IC, there is usually a diode from the output to the VCC of the logic IC. If any leakage current flows into the IC output when VCC is at 0 V will cause the output to be one diode drop above 0V. \$\endgroup\$
    – user57037
    Commented Sep 17, 2022 at 3:23
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  1. If your gate is off, its output will be 0V, and so will the FET gate be 0V.

  2. If the FET source or gate are at least one Vgs threshold above the gate, the FET will be on. So if your gate drive is 0-5V and your source is 12V, the FET will always be on. Likewise, if the gate is powered off, the FET gate is 0V and sour or drain are Vgs threshold or higher, the FET will be on.

To get the desired behavior, you may consider using an NFET to level-shift the PFET gate voltage. Then you can also ensure the PFET is off if Vcc is off.

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