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This book states that 'a thin-gate oxide is designed to achieve the high speed on and off switching of the MOSFET'. My understanding is that the on-off time of a FET is determined primarily by the gate capacitance of the FET (and of course the resistance in series and gate driver strength)

However, a thinner oxide (oxide is the dielectirc material) means the distance between the plates is smaller. That should increase the capacitance and hence increase the on-time. So how does a thinner oxide lead to faster on-off switching times?

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  • \$\begingroup\$ Took me seconds (I spent more time writing this line) to find this early paper on the topic. Have you read it? Also look for any papers that reference it. For example, "A circuit-level perspective of the optimum gate oxide thickness" is a 2001 paper that does. \$\endgroup\$
    – jonk
    Sep 15, 2022 at 19:10
  • \$\begingroup\$ Thinner oxide allows lower voltages to be used to switch the gate. Less voltage on the capacitor means faster switching time. It could also mean (and I don't know this for fact) that the area of the transistor could be made smaller... that could be counteracting the increased capacitance from the thinner oxide layer. Caveat - I studied it in College, I am not a chip designer today.... \$\endgroup\$
    – Kyle B
    Sep 15, 2022 at 20:53

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You are right that the gate capacitance is an important factor of transistor "speed". However, there are other effects that can change it.

A thinner oxide will typically reduce the threshold voltage, which will cause a higher current for the same input voltage, or in other words: the output resistance \$R_{ds}\$ of the transistor will decrease. The switching speed of logic is approximately proportional to the \$R_{ds}C_{gate}\$ time constant, meaning that reducing \$R_{ds}\$ might indeed make it faster.

I took a look at the paper that jonk referenced in the comments, and the conclusion of it is that changing the oxide thickness can affect the switch time in both ways (positively or negatively) - there is an optimum. For larger thickness, \$R_{ds}\$ will have a bigger effect, while for smaller thicknesses the gate capacitance has a bigger effect.

In practice more things are at play as foundries first want to provide a general-purpose transistor. Gate leakage, breakdown of the gate, lifetime, yield, etc. likely push the gate oxide thickness to higher values, which means that we are going to be in the situation of the book where he then proceeds to highlight a few of the issues of why a thin-gate transistor is not a free lunch.

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