Does anyone know how to build the resettable integrator in SIMPLIS or PSIM simulation?

The figure below is from IRF

I would like to do an OCC control for PFC, but I get into some trouble with how to do it. How can I reset the integrator? Does this affect the control loop bode plot?

enter image description here

update :

I add my simulation there. enter image description here enter image description here

John D method: enter image description here

  • 1
    \$\begingroup\$ I'd imagine you could make a conventional op-amp integrator and put a simple SIMPLIS switch across the capacitor to reset it. \$\endgroup\$
    – John D
    Commented Sep 17, 2022 at 18:02
  • \$\begingroup\$ Hi @JohnD, I update the circuit in my content, do you meant that? \$\endgroup\$
    – Jitter456
    Commented Sep 18, 2022 at 1:27
  • \$\begingroup\$ @Jitter456 Yes, both methods are valid: mine deals with a behavioural approach, JohnD's with a more practical one. it depends on what you want: to model the IC or to see a quasi-real approach. \$\endgroup\$ Commented Sep 18, 2022 at 8:47

1 Answer 1


If there isn't an equivalent of a behavioural voltage source then you can do it if you have a sample & hold block. Looking over at their documentation it looks like there is one but, it's marked as obsolete. I presume there is a newer one.

I'm saying this because, in LTspice, you can do this:

resettable integrator

V1 is a sine input, G1 is a VCCS that, together with C1 act as an integrator. A1 is the S&H block which is activated on the rising edge of V2. The sampled waveform is subtracted from the continuous-time integrator output, resulting in a resettable integrator. The output is compared to the much simpler behavioural expression in B1. I think the idt() implementation is particular to LTspice, because the way it's written it integrates V(in) and resets it to zero everytime the positive values of V(clk)'s derivative goes above 0.5 V (if used without the derivative the reset would happen for the entire duration of Ton; this way it only lasts for the duration of the rise time).

At any rate, SIMPLIS seems to have the S&H block active on the rising edge so the schematic should be able to be implemented and work as it does in LTspice. In terms of elements/nodes it is a little bit expensive but, it should work with minimal impact since it's made with primitives which are linear. Only the clock might pose a threat, depending on its parameters.

What I showed can provide a true resettable integrator, e.g. the output will go to zero exactly the moment it is reset, not after some time constant. This may be desirable in behavioural studies, as opposed to modelling an "analog resettable integrator" (e.g. a capacitor with a JFET). But if you need the falling edge to have its own, discharging time constant then you can use a switch (much like what @JohnD proposed):

reset with VCSW

G2, C2 form the integrator. If your program has a block for an integrator instead of what I'm using then you can use that but, take care that its output allows the reset (here it's a current source thus, "infinite" output impedance). Comapared is the voltage from a behavioural expression -- they are almost identical, save the minor 1 ms time constant for discharging.

  • \$\begingroup\$ If you need to have the output reset for the entire duration of Ton then use the S/H input for the clock in A1. This is in LTspice but, if the SIMPLIS block allows it... Also, about the cost, it just occured to me that, unless you have bought SIMPLIS, the demo only allows for some 10(?) maximum states, which means that this approach will use two (the capacitor and the S&H). So it's pretty expensive in that regard. \$\endgroup\$ Commented Sep 17, 2022 at 20:24
  • \$\begingroup\$ I try to use the PSIM sample and hold function to do that, but I don't know why in your circuit you can reset the output. if the A1 is a sample and hold circuit. and why you need also to add a E1 in the circut? \$\endgroup\$
    – Jitter456
    Commented Sep 18, 2022 at 1:22
  • \$\begingroup\$ @Jitter456 Have you read the explanation? The S&H block only samples and, when it does that, the value of that sample will be exactly the same as the continuous-time integrator's at that instance of time. Which means that, subtracting the two will give a zero at that time. So E1 performs that subtraction. Does it work in PSIM/SIMPLIS? \$\endgroup\$ Commented Sep 18, 2022 at 7:13
  • \$\begingroup\$ I update the simulation, Do S&H and subtractor are using to do the resettable integrator? \$\endgroup\$
    – Jitter456
    Commented Sep 18, 2022 at 8:18
  • \$\begingroup\$ @Jitter456 I don't understand -- you built the circuit, you can see for yourself the results of the simulation, yet you're still asking me if "it has to do with the resettable integrator"?! Have you not read anything I wrote? Are you not able to tell if what you're simulating has the expected output? Do you know how a resettable integrator is supposed to behave? Because, if you don't, it means you simply don't understand what you're doing. \$\endgroup\$ Commented Sep 18, 2022 at 8:45

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