MOSFET gate failure caused by unknown reason

Question

I have the below circuit (link to simulation). It represents the low-voltage interlock and high-voltage precharge & discharge circuit for my Formula SAE team's EV car. While most other FSAE teams use a normally-closed relay for the discharge circuit, our alumni have opted for a "self-closing" n-MOSFET circuit, since it has a smaller footprint. When the interlock opens, the capacitor activates the MOSFET's gate until voltage drops down to V_GS(th), which is sufficient on paper. The Zener diode is meant to limit the gate voltage below V_GS(max) during this process.

The discharge circuit's purpose is to allow the high-voltage capacitor to discharge thru a chassis-mount resistor. As per FSAE rule EV.8.2.2, the high-voltage side must drop below 60 V within 5 seconds of opening the interlock. In the simulation, this is all fine and dandy, that voltage being reached within 3 seconds.

However, in real life, it takes nearly 10 seconds. I think I have narrowed down the issue to the MOSFET gate failing, for an unknown reason. On 2 removed MOSFETs, I have measured internal R_GS values of 4 kΩ and 38 kΩ, which seems to indicate part damage.

I tried 3 different models of MOSFET, but the problem remains. The part I currently have is AOD7N65, which seemed to satisfy all requirements when I picked it. Peak discharge current is about 170 mA, which is within that part's safe operating area for 400 V.

So, the big question; why is the MOSFET failing? Am I missing something? Any help is appreciated.

Answer 1

Based on the gate-source voltage and resistance measurements, \$|V_{GS}|\$ is exceeding 30V. In your circuit the only way this can happen is with the FET's internal inductance in series with the source, \$L_{S}\$ and with the gate \$L_{G}\$. There is a capacitance \$C_{GS}\$ between the gate and source. The voltage on this capacitor holds the transistor on and must be discharged to turn it off. There is source current at turn-off time.

\$L_{S}\$, \$L_{G}\$, \$C_{GS}\$ and \$C_{Z}//C_{CE}\$, of the opto-isolator, form a series resonant circuit damped by by the gate spreading resistance \$R_{G}=5\Omega \$.

This will resonate at 10s of megahertz. A low bandwidth scope may not see this. Placing a scope probe to measure \$V_{GS}\$ will add another capacitance into the mix.

Turning the FET on or off will excite this resonance. The voltage across the capacitor will rise to a high voltage based on resonant rise of voltage for series resonance. The only solution is to damp it out.

The lower figure shows a damping resistor of about 1k. This is a guess, but should work. It can be calculated for a Q of 0.5 or less.

^{simulate this circuit – Schematic created using CircuitLab}

^{simulate this circuit}

A final note: If the switch that operates the opto-coupler bounces then the FET will turn on and off several times. Each time could result in a high \$V_{GS}\$, take steps to de-bounce the switch.

This is a speculative answer that is waiting for testing. Let us know what finally works.

Answer 2

The gate capacitance is around 1 nF and you have a 4.7 MΩ resistor. Thus the turn of of the MOSFET will be slow. As well, there's the leakage of the Zener to consider.

When simulating the circuit, observe the SOA parameters of the MOSFET (figure 9 of the datasheet). You may be be suffering from the 'Spirito effect'. This may occur during the turn on phase or during the discharge phase where the MOSFET may not be fully driven.

[edit] At a glance, it does seem you are well within the SOA requirements. How about temperature? Initial disipation is 400 * 0.16 = 64 W. Without heatsinking, the device might overheat.