I have the below circuit (link to simulation). It represents the low-voltage interlock and high-voltage precharge & discharge circuit for my Formula SAE team's EV car. While most other FSAE teams use a normally-closed relay for the discharge circuit, our alumni have opted for a "self-closing" n-MOSFET circuit, since it has a smaller footprint. When the interlock opens, the capacitor activates the MOSFET's gate until voltage drops down to VGS(th), which is sufficient on paper. The Zener diode is meant to limit the gate voltage below VGS(max) during this process.

The discharge circuit's purpose is to allow the high-voltage capacitor to discharge thru a chassis-mount resistor. As per FSAE rule EV.8.2.2, the high-voltage side must drop below 60 V within 5 seconds of opening the interlock. In the simulation, this is all fine and dandy, that voltage being reached within 3 seconds.

However, in real life, it takes nearly 10 seconds. I think I have narrowed down the issue to the MOSFET gate failing, for an unknown reason. On 2 removed MOSFETs, I have measured internal RGS values of 4 kΩ and 38 kΩ, which seems to indicate part damage.

I tried 3 different models of MOSFET, but the problem remains. The part I currently have is AOD7N65, which seemed to satisfy all requirements when I picked it. Peak discharge current is about 170 mA, which is within that part's safe operating area for 400 V.

So, the big question; why is the MOSFET failing? Am I missing something? Any help is appreciated.

Interlock and discharge circuit

  • 1
    \$\begingroup\$ If the discharge time is that long, some oscillation may be present. I would try a 16 V Z-diode for more distance to the plateau voltage and probably 1 nF parallel to it as a second step. \$\endgroup\$
    – Jens
    Sep 18, 2022 at 13:13
  • \$\begingroup\$ @Jens - I think the long discharge has more to do with gate damage. At the instant the relay opens, I measured only a mediocre 0.2 V at VGS, as opposed to the intended 8.2 V. Afterwards, I unsoldered the MOSFET, and measured 4 kΩ at RGS, which is totally abnormal. I'm starting to think that since the HV side is floating when the relay is open, there must be a damaging transient spike occurring at closure, which is weird because that's exactly what the capacitor is supposed to prevent. Maybe I should put an HV diode between the MOSFET's source and the precharge resistor? \$\endgroup\$
    – AgentRev
    Sep 18, 2022 at 17:49
  • \$\begingroup\$ One thing I notice is that you're operating the FET at a lower gate voltage than it's designed for; the on-resistance shown in the datasheet is given at 10 V and you have an 8 V zener. Still, I would expect the FET to be mostly on at 8 V, so I doubt that's the ultimate source of the problem. \$\endgroup\$
    – Hearth
    Sep 18, 2022 at 18:10
  • \$\begingroup\$ @AgentRev: Can you provide the datasheet for the 340uF capacitor and the optocoupler that you are using? \$\endgroup\$
    – RussellH
    Sep 18, 2022 at 20:03
  • \$\begingroup\$ @RussellH - capacitor: content.kemet.com/datasheets/KEM_F3059_C4DE.pdf and optocoupler: toshiba.semicon-storage.com/info/… \$\endgroup\$
    – AgentRev
    Sep 18, 2022 at 20:32

2 Answers 2


Based on the gate-source voltage and resistance measurements, \$|V_{GS}|\$ is exceeding 30V. In your circuit the only way this can happen is with the FET's internal inductance in series with the source, \$L_{S}\$ and with the gate \$L_{G}\$. There is a capacitance \$C_{GS}\$ between the gate and source. The voltage on this capacitor holds the transistor on and must be discharged to turn it off. There is source current at turn-off time.

\$L_{S}\$, \$L_{G}\$, \$C_{GS}\$ and \$C_{Z}//C_{CE}\$, of the opto-isolator, form a series resonant circuit damped by by the gate spreading resistance \$R_{G}=5\Omega \$.

This will resonate at 10s of megahertz. A low bandwidth scope may not see this. Placing a scope probe to measure \$V_{GS}\$ will add another capacitance into the mix.

Turning the FET on or off will excite this resonance. The voltage across the capacitor will rise to a high voltage based on resonant rise of voltage for series resonance. The only solution is to damp it out.

The lower figure shows a damping resistor of about 1k. This is a guess, but should work. It can be calculated for a Q of 0.5 or less.


simulate this circuit – Schematic created using CircuitLab


simulate this circuit

A final note: If the switch that operates the opto-coupler bounces then the FET will turn on and off several times. Each time could result in a high \$V_{GS}\$, take steps to de-bounce the switch.

This is a speculative answer that is waiting for testing. Let us know what finally works.

  • \$\begingroup\$ Interesting theory. I had a hunch it has to be some kind of weird interaction like that. I will add a 1k resistor to the gate of AOD7N65 this week, and will test back for damage in a few weeks. Thanks for the analysis! \$\endgroup\$
    – AgentRev
    Sep 19, 2022 at 1:32
  • \$\begingroup\$ Seems to have fixed the problem! We had a track day last week, during which the discharge circuit was triggered dozens of times, and discharge time always stayed within 3 seconds. However, I think there might still be some light damage to the gate. With a brand-new MOSFET soldered before track day, I measured a Thevenin RGS of 44 MΩ, and earlier today, I measured a Thevenin RGS of 7 MΩ. So maybe I should increase the resistance just to be sure. \$\endgroup\$
    – AgentRev
    Oct 14, 2022 at 2:26
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    \$\begingroup\$ @AgentRev: Be careful using an ohmmeter to measure the gate-source resistance. You may damage the gate by handling it this way. 44M seems a low to me. Should be giga-ohms. I can be corrected. Handling this way can easily create a static discharge of much greater than 30 V. \$\endgroup\$
    – RussellH
    Oct 14, 2022 at 2:46
  • \$\begingroup\$ I see, thanks for the tip. When I measured RGS before soldering the MOSFET, ohmmeter said "open". The 44M measurement is after I soldered it (Thevenin resistance measured at RGS). This is the value that dropped to 7M after track day. I'm thinking about increasing the gate resistor to 10k. \$\endgroup\$
    – AgentRev
    Oct 14, 2022 at 16:19

The gate capacitance is around 1 nF and you have a 4.7 MΩ resistor. Thus the turn of of the MOSFET will be slow. As well, there's the leakage of the Zener to consider.

When simulating the circuit, observe the SOA parameters of the MOSFET (figure 9 of the datasheet). You may be be suffering from the 'Spirito effect'. This may occur during the turn on phase or during the discharge phase where the MOSFET may not be fully driven.

[edit] At a glance, it does seem you are well within the SOA requirements. How about temperature? Initial disipation is 400 * 0.16 = 64 W. Without heatsinking, the device might overheat.

  • \$\begingroup\$ I picked AOD7N65 specifically for its SOA, since the previous part had an inadequate SOA. Heat dissipation in the MOSFET itself is a few milliwatts. Most of the heat is produced thru the 2.5 kΩ chassis mount 100 W resistor connected at the drain, causing a significant voltage drop when MOSFET turns on. Another clue; part IRFBC40S seems to work fine in this circuit, with its RGS remaining open after weeks of regular operation. The only issues are that it's the wrong footprint for my existing PCB and that the root cause is probably still lurking in the shadows. \$\endgroup\$
    – AgentRev
    Sep 18, 2022 at 8:40

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