I have a Verilog design for a Basys 3 in which I display a number increasing by 1 each half second in a 7 segment display.
I'm running the timing analysis in Vivado, and I get a hold time violation caused by an async. reset, let me explain:
The blue path is the one that causes the violation.
- The main clock (sys_clk onwards) is
CLK100MHz_IBUF_BUFG. This is the Basys 3 main 100 MHz clock.
dfis a debounce filter.
cdsare clock dividers. As you see,
cdis clocked by
cd/clk, which is
- The reset signal comes from an FPGA button, however it is passed through a debounce filter. Therefore, the
rstsignal depicted above will be synchronous with regards to
sys_clkI suppose, and it will be so with regards to the others two given that they match the phase of
sys_clk. If FPGA button that causes the reset would be pressed 'quick enough' I imagine it could generate a pulse that causes a setup and hold violation, but given that
sys_clkis 100 MHz this is not humanly possible.
While I get a hold time violation, I think the actual problem is that
df, which is clocked by
sys_clk, and goes into
cds (clocked by a different clock) and Vivado thinks this could cause a meta state. That would explain why there is no violation at
I want to set this as a false path because I know that the
rst signal is asynchronous in
cds and therefore there can't be a meta state. Is this reasoning correct?
Edit: the explanation above is wrong because the signal is not actually asynchronous, it is a multiple of
sys_clk and matches it phase. Then why do I get a hold violation?
PD.: Here is the error report:
Edit - possible fix
I tried to reduce the problem by removing the reset signal here. This gets fixed by setting both clock signals a physically exclusive. It turns out that it fixes the problem described in this post as well.
However, I don't think in this case these 2 clocks can be set as physically exclusive, let me explain:
My clock interaction report is now:
This is interesting because, unlike the link provided above, there is now a new clock interaction
cd/clk (bottom left).
This occurs as a consequence of changing the reset in the flip-flop
c (see schematics below) from
1'b0 (which is how it is in the link above), to
rst. I have inspected the schematics:
Unlike the schematics in the link above, there is now a path from
AR, the reset signal). I think this is from where the above clock interaction come, and I think technically it can't be told that these two clocks are physically exclusive, because a signal coming from a module (
df) clocked with
CLK100MHZ goes to a module (
c) clocked by
clk, which is a different clock. Is this correct?