I am confused as to when the '-' sign is used and when 's' is used. This post is somewhat helping, although not entirely.
Please correct if I am wrong:
For example, to interpret 8'sd244, we write 244 in binary = 11110100. Now it is signed, so the MSB tells us that it is a negative number. So the remaining bits are in 2's complement form, so the actual number stored is -12.
Now when we declare -16'h3A, this is actually 16'hFFC6 in 2's complement form. So declaring these should be equivalent. But how does Verilog know that 16'hFFC6 must be interpreted as a 2's complement number?
In other words, are the below the same?
a = 16'hFFC6;
a = -16'h3A;
Is it different in SystemVerilog and Verilog?