In my high frequency supply my MOSFET VDS signals seem to be falling/rising at much slower rates than the data sheet would suggest for a Gallium Nitride switch: https://www.ti.com/lit/ds/symlink/lmg3410r050.pdf?ts=1663639229270.

I have a custom transformer in an active clamped flyback circuit that seems to be quite high capacitance, and I am also operating the converter at a voltage level slightly lower than that recommended in the data sheet simply for safety reasons. I plan to increase the applied voltage when I can.

The rise and fall-times are 25 and 60 ns, respectively. The much slower rise and fall times cause the VDS signals to overlap and seems to cause some hard switching in the circuit when everything should have soft switching. I have tried to increase the dead-time between the switches, but this will still lead to soft-switching when the main switch VDS is not clamped causing ringing on the main flyback FET. I also have the suspicion that my clamp capacitor is too large as the waveforms look a little different than what would be expected with an active clamped flyback when the main FET is off.

I'd like to be able to calculate the effective capacitance across the two FET's depending using the rise and fall-times and the applied VDS I can see on the scope, but am not entirely sure where to start with this.

Any thoughts?

Flyback VDS (dark blue), clamp VDS (light blue), output diode (green) and final DC output voltage (purple) waveforms

  • \$\begingroup\$ Unclear without a schematic. \$\endgroup\$
    – DKNguyen
    Sep 20 at 15:35
  • 1
    \$\begingroup\$ This could be caused by any number of things. Please provide a schematic, show the relevant area of board layout, and describe your measurement setup. \$\endgroup\$
    – Polynomial
    Sep 20 at 15:52
  • \$\begingroup\$ Apologies, will post a schematic tomorrow first thing. Thanks for the comments. \$\endgroup\$
    – jvnlendm
    Sep 20 at 17:35

1 Answer 1


No, the rise time is a sum/product of many different parasitic elements in a mosfet. If you look below there are several elements (Cgd and Cgs being large contributors) as well as the inductance of the pins and wires and silicon in the mosfet. You could assume that all of the rise time contribution is from Cgd and Cgs, at really fast speeds the other parsitics will come into play.

enter image description here

Source: https://www.researchgate.net/figure/Generic-circuit-model-of-the-MOSFET-transistor_fig1_3280902

  • \$\begingroup\$ I understand this, but I think that in the active clamp the transformer capacitance also contributes to the rise and fall times of the FET. I’d like to be able to show that theoretically somehow. Thanks for the comment! \$\endgroup\$
    – jvnlendm
    Sep 20 at 17:36

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