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The LDO datasheet usually specifies the maximum output capacitance for stability reasons. I wonder if this capacitance is meant for the entire power plane or just the capacitor right at the output of the LDO. For the power plane, there may be other decoupling capacitors on the IC sides. Are those capacitors included?

For example, this LDO has 10 μF maximum capacitance.

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All the LDO cares about is the impedance at its output pin. In particular, the impedance at frequencies near cutoff.

For example, if your circuit has bypass caps spread about indiscriminately, preferably joined together on a power/ground plane pair: the impedance will be very low, the components acting essentially in parallel at any frequency the LDO cares about. Thus, the total figure should be used.

Cutoff frequency can be inferred from the PSRR and Zout plots (if provided), typically in the 10-100 kHz range. For this part, looks about 2-3 MHz.

The character of that impedance can be controlled by filter or "isolation" networks. A series resistor obviously increases AC resistance, though it increases DC resistance (worsening load regulation) as well. Putting a large inductor in parallel with said resistor, affords low DC drop, but controlled AC resistance. A suitable capacitor can then be placed local to the regulator. Finally, the inductor needs to be dampened, by choosing \$R=\sqrt{L/C}\$, and/or putting a R+C (lossy "bulk" capacitor) in parallel with the load side.

Other topologies are relatively easy to analyze; for example, if using point-to-point routing instead of planes, the stray inductance between points (loads with local bypass cap(s)) creates a lowpass filter or lumped-element transmission line effect, and such a line should be terminated at the far end with a bulk capacitor.

The important realization is to consider the power supply as an RLC network. Then, cutoff frequencies, attenuation factors, impedances and damping factors (and corresponding ringing, or the adequate prevention thereof) can be understood. SPICE for example can be used to model a given network, and values adjusted to give suitable impedance at each point in the circuit.

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I wonder if this capacitance is meant for the entire power plane or just the capacitor right at the output of the LDO.

The data sheet says this: -

enter image description here

And I take that to mean that you can distribute your output/load capacitance in various places on your PCB. So I would use a 1 μF close to the chip and allow up to a further 9 μF to be distributed around various circuits on your PCB.

See also this section in the data sheet: -

enter image description here

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