My understanding of a flash-ADC is that it simultaneously compares an input voltage to a ladder of reference voltages using multiple voltage comparators. When used in a fast digitizer, the comparison is repeated at the sampling frequency of the device (say GHz).
If this is right, only the voltage at the precise sampling time is taken into account, and the voltage that happens to fall between samples is not a factor.
Is this is correct, or are things more complicated, and is it in fact the integral of the voltage between samples that plays a role? For instance, does a digitizer with a flash-ADC sampling at 10 ns really just compare the voltages at an instant every 10 ns, or is there some capacitor charging in the voltage comparators, meaning that the full 10 ns history of the voltage play a role?
My example is of a signal that contains several random bursts, 5 ns long. If I sample at 1 ns, then numerically calculate the integral (sum of samples × 1 ns), I get a given value. If I repeat this with 10 ns sampling, I think I would miss most of the burst information, and the integral would be quite different, unless the voltage comparators in the flash-ADC have some hidden integration in them.