My understanding of a flash-ADC is that it simultaneously compares an input voltage to a ladder of reference voltages using multiple voltage comparators. When used in a fast digitizer, the comparison is repeated at the sampling frequency of the device (say GHz).

If this is right, only the voltage at the precise sampling time is taken into account, and the voltage that happens to fall between samples is not a factor.

Is this is correct, or are things more complicated, and is it in fact the integral of the voltage between samples that plays a role? For instance, does a digitizer with a flash-ADC sampling at 10 ns really just compare the voltages at an instant every 10 ns, or is there some capacitor charging in the voltage comparators, meaning that the full 10 ns history of the voltage play a role?

My example is of a signal that contains several random bursts, 5 ns long. If I sample at 1 ns, then numerically calculate the integral (sum of samples × 1 ns), I get a given value. If I repeat this with 10 ns sampling, I think I would miss most of the burst information, and the integral would be quite different, unless the voltage comparators in the flash-ADC have some hidden integration in them.

  • \$\begingroup\$ Image failed to attach. But without the image and from words alone, there is always a parasitic input capacitance, even if one has not been added. And nothing ever happens instantly just like it doesn't with a SAR ADC, yet the sample is treated as an instant. So by your definition ever ADC is an integrating ADC in one way or another. I imagine no one purposely adds sampling capacitance to a flash ADC though since it would just slow it down and defeat the only reason you would select a flash ADC. \$\endgroup\$
    – DKNguyen
    Sep 21, 2022 at 19:34
  • \$\begingroup\$ @DKNguyen thanks, have clarified question \$\endgroup\$
    – Mister Mak
    Sep 21, 2022 at 19:40
  • \$\begingroup\$ @MisterMak as with most ADCs you need an anti-alias filter. \$\endgroup\$
    – Andy aka
    Sep 21, 2022 at 19:54
  • \$\begingroup\$ With regards to your edit, I would argue that perhaps you have not specified an appropriate ADC. But it's tough if you can't find anything suitable. If you're doing what I think you're trying to do then you would need to add a known and stable, known capacitance overwhelm whatever parasitic is there and then mathematically compensate by knowing the drive characteristics of your source. Because if the parasitic capacitance is large enough that you need to consider it to be integrating, then you might as well have it integrating in a known fashion so you can work with it. \$\endgroup\$
    – DKNguyen
    Sep 21, 2022 at 19:55

1 Answer 1


In principle, yes, a flash ADC is only interested in the input at the precise sampling time.

There are flash ADCs that are promoted as 'high IF sampling', or some similar description. They are designed with very short sampling windows so that they can down-sample an input signal which has a centre frequency above fs. However, used in this mode, they tend not to perform as well as when operating on a signal in the normal first IF of DC to fs/2. They do have some finite impulse response / a finite bandwidth, so there is some spreading out of the sampling moment in time.

When a flash ADC is preceded with a proper anti-alias filter, it's the memory of the filter, its impulse response, that governs the sampling time spread.


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