# Differential amplifier with active load current mismatch

From: Design of Analog CMOS Integrated Circuits by Behzad Razavi

The author mentions in Fig 5.26(c) that if a positive change is applied to the gate of M1 and an equal and opposite change is applied to the gate of M2, node F will fall. Thus, M4 pushes more current and M2 pushes less current, causing node VX to rise.

How does this make sense? The current through M4 and the current through M2 are the same, so how can one increase and the other decrease?

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Consequently, $$\I_{D1}\$$ increases, $$\V_F\$$ falls, and $$\I_{D2}\$$ decreases. Thus, the output voltage rises by means of two mechanisms listed below. Should Vout not change, we would see:

1. M2 draws less current from X to ground(because the absolute value of the NMOS M2 gate voltage is decreased) and

2. M4 pushes a greater current from VDD to X(the absolute value of the PMOS M4 gate voltage$$\V_{GS.M4} = V_{DD}-V_F\$$is increased, because$$\V_F\$$falls).

The only way to restore the equality of M2/M4 drain currents is through increasing Vout, so that the finite output resistances would balance uneven contributions of VCCS's (voltage controlled current sources) of the respective NMOS/PMOS transistor models. The directions of these VCCS's are opposite, and, with Vout increasing, the shunt $$\r_{O2}\$$would increase the total drain current of M2, while the shunt$$\r_{O4}\$$would decrease the total drain current of M4. With the required Vout increase, the total M2/M4 drain currents become equal.

By contrast, in the circuit of Fig.5.23(a), ...

You may raise objection to this interpretation saying the omitted text is greater in volume than explicitly given. Re-read the previous sections of the book, maybe you've been browsing the book a bit hastily and lost the context.

Very helpful is to simulate the circuits where text explanations confuse you and analyze the computed currents/voltages. To err is human, but simulators do not lie ;).

• Excellent response. Another question, the actual values of ro_4 and ro_2 would change in this case, correct? If we assume that the change applied at the input devices is considered large-signal (which I believe it is, given the context), then the small-signal output resistances would also vary with this. Commented Sep 23, 2022 at 18:41
• As far as I'm aware, Ro's of the devices can only be used in small-signal analysis. Commented Sep 23, 2022 at 22:33
• Of course, Vin might be large signal, but is it really necessary to analyze the large signal at the diff pair inputs? Think about the output voltage swing of the diff pair. Even with a 10dB gain (10x) you can reasonably use small aignal approximation to estimate the transistor parameters required: at the output, the input signal should be amplified, not distorted. Notice also that a small gain on the input stage of three stage opamps implies a small output signal fed to the high-gain stage, so the small signal approximation can be used in this case, too. Commented Sep 24, 2022 at 6:09
• If you still need to do manual calculations with large input signals, you can mimic simulators in doing this: calculate an initial operation point and move input signals to a desired value by increments small enough to validate the use of small signal approximation at each step. Commented Sep 24, 2022 at 6:10
• I see, so you're saying that even with large-signal inputs, using a small-signal model can still give us an insight on what's going on. The reason I am confused is because looks to me like these are large-signal changes and your answer is relying on the small-signal r_outs to justify where the difference in current is flowing. Commented Sep 24, 2022 at 11:05

Let’s look at this by a simple way

NB: All delta variation on the are small signal variations around a quiescent point

You apply a small positive delta V on M1 and equal opposite amount on M2

regarding only M2 as a Nmos common source ( check small signal gain of common source ) stage with M4 as load , you can see that as the voltage apply to M2 is a small (let’s say negative) Delta V , so the voltage at the node X will go on the opposite direction (so here positive direction) M2 want to draw less current and we can say roughly that M4 (remember M4 is tie to VDD)start to take the control of X.

By the same way , as positive Delta V is apply to M1 that create a Delta I on the branch M1-M3, thus vgs of M3 fall (it’s Pmos so more it go down more he can inject current) as gate of M3 and M4 are tie together Vgs of M4 fall also and so you can now look this as a Pmos common source stage with M2 as load (if Vgs fall , so node X want to go up) and thus the rising of node X permit to restore same current into M2 and M4

This two signal path enhances each others because this two change have the same polarity

The current through M4 and the current through M2 is the same, how can one increase and the other decrease??

The answer previously given is incorrect and is deleted.