Here's a simplified efuse diagram:

enter image description here

Here is the efuse configurations in my circuit: enter image description here

The load is not present on this pcba. There is a 100mm long cable connecting this board to the load which is a standalone computer.

Besides doing fuse like protection these devices will also help softstart the output by controlling how much current flows through the FET during the initial turn on phase. Obviously the faster it turns on the more inrush the system will experience.

Here is a waveform for the inrush and output rising using this chip (blue is current and green is voltage rising to 12V): enter image description here

Now by slowing the turn on the inrush would reduce i get that. However the chip is able to handle this inrush (within its SOA) and the output is not affected by it either.

However why do we see so much voltage droop on the output. If i added a larger output cap would that reduce the voltage droop? I imagine the inrush to increase further by adding more output capacitance but would that reduce the spikes seen on the green voltage waveform?

  • 1
    \$\begingroup\$ Hi, (a) "why do we see so much voltage droop on the output" Just to be clear, what you're calling droop - are those the brief, sharp dips on the green (voltage) trace, each time the blue (current) trace hits 6 A? (b) Can you please add your actual schematic, showing the specific R & C values used to configure that IC's behaviour? Thanks. \$\endgroup\$
    – SamGibson
    Sep 23, 2022 at 15:57
  • \$\begingroup\$ @SamGibson yes i mean the brief sharp dips. Also attached the efuse schematic \$\endgroup\$
    – Hasman404
    Sep 23, 2022 at 16:01
  • \$\begingroup\$ These voltage dips would be caused by stray inductance reacting to the inrush i imagine. The efuse connects to the load over a cable. So perhaps making that as short and twisted as possible could help. But adding output capacitance to the efuse would help too no? \$\endgroup\$
    – Hasman404
    Sep 23, 2022 at 16:02

1 Answer 1


I suspect you might be reading the wrong datasheet, because your first image is of a TPS1663x whereas your circuit shows a TPS26631. The TPS26631 you are using does not include a power limiting (PLIM) feature. This is only present on the TPS26632, -3, -5, and -6 models.

Your \$C_{out}\$ seems far too small here. Your \$C_{in}\$ is also the bare minimum recommended.

For a load of 6A, your 11µF output capacitance will discharge by 5V after just 9.1µs:

$$t=\frac {CV} {I} = \frac {11\mu F \times 5V} {6A} = 9.166\mu s$$

The datasheet indicates that the internal MOSFET will be briefly turned off under a range of overcurrent scenarios. The turn-off time for overcurrent events below the hot-short (45A) limit is between 2.2µs and 4.5µs.

The typical applications and other calculations in the datasheet indicate that output capacitances in the order of 1000µF are appropriate here.

Additionally, plugging your \$C_{out}\$ and \$C_{dVdT}\$ values into the calculations in section 9.3.1 of the datasheet further demonstrates that your output capacitance is far too low:

$$I_{INRUSH} = C_{out} \times \frac {V_{in}} {t_{dVdT}}$$


$$t_{dVdT} = 20.8\times10^3 \times V_{in} \times C_{dVdT}$$

Plugging your values in, that gives us:

$$I_{INRUSH} = 11\mu F \times \frac {12V} {20.8\times10^3 \times 12V \times 0.33\mu F} = 1.6mA$$

Which is obviously not correct.

  • \$\begingroup\$ The 11uF seen in the schematic is not the load though. It's more for transient protection. The load is not on the PDB but rather an off the shelf frame grabber. The inrush seen in the waveform is a result of that. \$\endgroup\$
    – Hasman404
    Sep 23, 2022 at 19:57
  • \$\begingroup\$ It would have been helpful to include that information in your question. If the load is all the way down the cable and you're measuring at the supply end, these transients are likely due to stray inductance and might be utterly meaningless. \$\endgroup\$
    – Polynomial
    Sep 23, 2022 at 20:12
  • \$\begingroup\$ Apologies i've updated the post but why would they be meaningless? The load appears to not like the large voltage dips seen here and goes into reset. \$\endgroup\$
    – Hasman404
    Sep 23, 2022 at 20:16
  • \$\begingroup\$ @Hasman404 You hadn't mentioned that, either. Given the lack of information I can't really offer much more insight - only speculation. It'd be helpful if you would edit your question to provide a full description of the fault behaviour, information about the load, a more complete schematic (where are the UVLO, FLT, OVP, etc. lines going?), and how you derived the component values. \$\endgroup\$
    – Polynomial
    Sep 23, 2022 at 20:26

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