I am designing a 2 layer PCB with high speed signals (200 MHz range) AND 4 layer PCB is NOT an option. Which of the following would be a better scenario for signal integrity, and if possible, explain why?

  1. Bottom layer as ground plane, Top layer signal
  2. Bottom layer as ground plane, Top layer signal with power pour
  3. Bottom AND Top layer as signal, with all signals and power tracks having a ground track just adjacent to it as differential pairs
  4. Bottom AND Top layer as signal with ground pour, with all signals and power tracks having a ground track just adjacent to it as differential pairs

To my understanding, 3rd scenario should perform the best as it would keep all displacement currents in check and kill most cross-talk. (Keeping in mind to have a good decoupling capacitor population to minimize switching loads of components).

My reasoning for why 4th scenario might be worse than 3, even though it offers low impedance return path, is that sometimes signals would share/intersect return paths, creating ground bounce/offset/radiating noise into ground.


Lets add scenario:

  1. Bottom layer as ground plane, Top layer signal with ground pour
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    \$\begingroup\$ When you say "high speed signals (200MHz)", is that the clock rate or did you derive the fundamental frequency from the rise/fall time? \$\endgroup\$
    – Polynomial
    Sep 23, 2022 at 20:44
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    \$\begingroup\$ Fundamental frequency, signifying rise and fall times AND NOT clock frequency \$\endgroup\$
    – Bubu
    Sep 23, 2022 at 20:47
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    \$\begingroup\$ Good stuff - a lot of people get that wrong! I'll have a think about the details here and write up an answer in an hour or two. \$\endgroup\$
    – Polynomial
    Sep 23, 2022 at 20:51
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    \$\begingroup\$ What distance? What kind of logic drivers/receivers (CMOS, and what grade/family; LVDS; etc.)? How many nodes on the net? \$\endgroup\$ Sep 23, 2022 at 20:52
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    \$\begingroup\$ The AM6442 is (according to Google) a 441 pin BGA with PCIe and LPDDR4. Looking at the layout recommendations I see 8 layers or more. Possibly you can use fewer layers if you do not use most of its features, but then a less complex part might be both cheaper and much easier to implement on a 2 layer board. Are you sure you've picked the right SOC for the job? \$\endgroup\$ Sep 24, 2022 at 1:18

2 Answers 2


#2, approximately.

Transmission lines

This is the first thing to understand in circuit layout. A signal current flows in a trace, and draws a complementary "image current" on neighboring conductors, the sum of displacement current (change in electric field) and induced current (change in magnetic field).

When the distance to nearby metal is consistent (as for a prismatic shape of fixed cross-section), and the material is uniform, a fixed characteristic impedance and velocity factor results.

When the image currents flow largely in ground rather than neighboring traces, crosstalk is low and shielding is good.

The induced currents drop off exponentially with distance inside a metal (skin effect), so a surrounding metal shield (such as with coax cable) is very effective.

That shield can be opened up somewhat (e.g., imagine slitting the outer cylinder of a coax cable, opening up and laying it flat), given that you don't mind some of the internal field now leaks out into free space. This topological mutation gives microstrip transmission line, roughly speaking. Well, flatten the signal conductor and remove the dielectric on top, but those are minor differences as it happens.

In this open configuration, image currents drop off approximately inversely with lateral distance away from the trace. The best way to reduce crosstalk between traces is to increase distance between them.

Top-side ground helps, but isn't a strong effect by itself (more on that in a moment).

For digital logic, we aren't concerned about very much crosstalk. Typical CMOS thresholds are 30% of supply, so interference up to as much could be present, and only just exhaust the noise margin. As it happens, even for minimum design rules on typical 4-layer PCB, crosstalk is on the order of 10%, so it's not a big deal -- as long as adequate termination is present, of course. On 2-layer, it might be more like 15 or 20%. (I haven't run the numbers in a while, someone can fill in in the comments?)

Note that typical dimensions for 2-layer are 60 mil dielectric, and 7 mil trace width and space (so 14 mil spacing on centers). With say 1 mil thick conductors. The edgewise coupling happens to be pretty weak. Basically the conductors are quite thin, so there's not much facing area, fringing dominates, and a lot of the fringing field shorts off into the ground plane, even at fairly close dimensions like this.

For the same reason, coplanar ground has little effect. CPWG (Coplanar Waveguide with Ground: microstrip with top-side GND pour around) has about 15% lower impedance than microstrip of the same dimensions, for minimum trace/space. The coupling between trace and same-layer GND is fairly low.

Actually I suppose that should be more like 7% coupling per side, since CPWG is surrounded on both sides.

Note that CPWG should have stitching vias nearby, say within a lateral distance of up to several dielectric thicknesses. Note that vias very close by the trace (less than a dielectric thickness, say?), they further affect the impedance (reducing it). And since they can't be placed continuously, the impedance will no longer be constant, but vary, at frequencies on the order of the electrical length between vias. Such a via fence therefore has a cutoff frequency: an electromagnetic bandgap (EBG) structure. (Assuming the vias are placed perfectly periodically, of course.) For frequencies below that cutoff, the effect is to approximate a bathtub or trench sort of geometry, which merely reduces Zo a bit.

Anyway, for nearby traces, we can have a differential microstrip arrangement, and consider the coupling factor between them. Or we can introduce ground between them, making a sort of differential CPWG, or a chain of overlapping differential microstrips, i.e. trace 1 (signal 1) couples into GND (trace 2) into trace 3 (signal 2), and even if the GND trace is via-stitched to plane, some field still peeks through the gaps between vias, and thus from trace 1 to 3. Coupling is obviously lower than for the case with nothing inbetween, but since the unshielded case is already pretty good for digital purposes, we tend not to care.

Note that if the interposing GND trace is not stitched to plane, then it acts as a coupled transmission line stub. That is, it's the three-trace ("triplential" as it were?...nevermind) structure, with the middle trace shorted to GND at the ends (presumably there's a GND via placed at the ends of this bus, or if nothing else, the two signal traces diverge, and so the middle trace spreads out into a wider pour, where the sudden increase in width means a step decrease in Zo, which therefore approximates a short circuit to the same end). A double-shorted transmission line has λn/2 resonant modes, so will couple energy between the two signals flanking it, at corresponding frequencies (and also to space, since there's a little radiation coupling to microstrip as well). Since the coupling factor is modest (~10%), we expect the Q of such resonance to be comparable (i.e. ~1/(10%) or Q ~ 10). So we might end up with unexpectedly high coupling between the signals, in certain bands (corresponding to the resonances), which can affect signal quality.

So, we prefer to use stitching vias, spaced such that the cutoff frequency of the above effect is high enough not to care.

This groundwork laid, we can already make some observations of your proposed examples:

  1. The default standard, microstrip. Obvious downside: 2-layer board is quite thick (dielectric, height over GND plane) so we could potentially waste a lot of space getting isolation between traces, if we need it.

  2. The "approximately" I opened with, is this: either the power pour is well bypassed to GND plane (each bypass capacitor, with corresponding via, acts as a slightly longer stitching via -- note that component body length adds to via and trace lengths), or we use the trivial case of "power" = GND entirely (in which case we can just use stitching vias straightaway).

    The effect of via length is to increase stray inductance, or transmission line length, of the connection. So, extra length makes grounding somewhat worse, etc. (How this effects signal quality exactly, is complicated; basically I would suggest drawing out the equivalent circuit of the trace(s), planes, etc., or, well, building a circuit model of a fields problem is a right pain -- just simulate the damn thing, really.)

  3. This is unquestionably worse, because image currents carry to nearby traces top and bottom. Shielding is poor, because lateral (same-layer) coupling is quite weak (this is probably a bit surprising, but explains your initial preference).

  4. This is no different, we're just treating power traces as signals. Note we can follow the same signal quality analysis on the entire power net, which generally is relevant at lower frequencies (due to the loading effect of the bypass capacitors strewn about) but which is no less important for a high performance circuit. We can generally ignore transmission line effects here (again due to the low frequencies), and use trace and component stray inductance and other effects in a lumped equivalent circuit. This makes PDN (Power Distribution Network) analysis a plain old network analysis problem. Which, granted, isn't exactly trivial, but at least we don't need a field solver for it.

Accordingly, I don't make a distinction between #1 and #2 with respect to power: in that case I would prefer to route power as its own trace, of adequate width to carry required current, maybe plus some minimum width if I have reason to reduce stray inductance a bit further; and then local bypass capacitors effectively stitch it to GND plane at point-of-load, which you will appreciate is a much less tedious solution than stitching two whole-ass layers of a board together. :)

I have more layout notes and 2/4 layer compare/contrast in this external post: https://www.eevblog.com/forum/projects/pcb-top-and-bottom-pour-gnd-and-vcc/msg3522442/#msg3522442

Finally, to address the particular/present case:

  • I didn't check the datasheet but I'm guessing AM6442 has fairly peppy CMOS pin drivers (comparable to 74LVC at least, if not faster still?). This is a concern for signal quality and EMC in general, having ~1ns risetimes and thus significant harmonic content up to or beyond 500 MHz.
  • For trace lengths of 150mm, we expect to need to consider transmission line effects for risetime under say 2ns or so.
  • If your loads are high impedance (typical logic input pins), then a source termination resistor should be used. Choose R + Rpin = Zo. Pin resistance is typically 30-70Ω for CMOS drivers (but check the datasheet to be sure).
  • If you don't need high PRF / clock frequency, higher resistances can be used, which have the effect of reducing the leading edge and slowing subsequent rise, using the transmission line as an equivalent capacitance. Further attenuation can be had by using a ferrite bead instead (higher impedance at high frequencies, inductive characteristic doesn't sacrifice DC performance), especially in combination with a little filter capacitance (a 330Ω FB into a 100pF capacitor will strongly attenuate RFI range noise).
  • And I'm guessing your PRF isn't very high, as SN75176 top out at 10Mb or so, so this should be adequate.
  • If you needed higher rates and/or longer lengths, consider placing an LVDS transmitter very close beside the SoC, and a receiver near the isolator. (Or, special case if the encoding is DC balanced e.g. Manchester encoded: just feed it right into a transformer e.g. Ethernet magnetics. You'll still need an LVDS receiver on the isolated side to recover logic level for the RS-422 driver. Hm, the digital isolator may well be cheaper than commodity magnetics, heh.)
  • For LVDS, RS-422 and such, load termination is typically used. So, don't worry about anything special at the transmitter (aside from maybe a common-mode choke).

Load termination can also be used for CMOS logic signals, but has some issues:

  • Input thresholds are typically 30-70% VCC
  • Output resistance is substantial (30-70Ω?)
  • Pin drivers can be quite puny; FPGAs for example often limit DC current to a few mA, which may be the case for your SoC as well

If we simply attach a typical CMOS output pin to a transmission line with typical Zo ~ 100Ω, we lose a good ~30% of the amplitude. With source termination, we recover that as the reflection rebounds from the far end of the line; with load termination, it stays low. We need a narrower input threshold to receive this signal. A precision schmitt trigger like 74HC7014 could be used, or an array of comparators (supposedly... LVDS receivers can be abused in this way, tying IN_N to a reference voltage!). We also need to use a suitable driver: weak pins should be buffered with an external bus driver.

A historical example combining both techniques, is the ST506 drive interface. This used a ribbon cable, with TTL pin drivers, alternating signal and grounds assigned in the cable (note the similarity to the suggested alternating signal-GND planar layout -- on a cable with no ground plane at all, you do what you have to!), and a termination resistor plugged into the last drive in the chain (actually an asymmetrical voltage divider between VCC and GND, since TTL thresholds are closer to GND; helpfully, TTL drive strength is adequate to meet input thresholds with such a termination). This carried control signals (like step / advance track, enable, etc.). A separate cable, with differential (RS-422), carried the high-speed data from/to the read/write head amplifier. The data cable was point-to-point. Typically a control card had one control connector and two data connectors, for operating up to two drives at a time.

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    \$\begingroup\$ Nice write up. I especially liked your cautionary notes about arbitrarily putting a ground trace between signal conductors which, as you noted, can set up unanticipated resonances. \$\endgroup\$
    – SteveSh
    Sep 24, 2022 at 1:25
  • \$\begingroup\$ This is a very good information. This is also a lot to process, give me some time to understand and make sense of it. Ill admit I am overwhelmed with this, The only thing I understand is a I have a lot to learn. I don't know why they don't this in schools :) \$\endgroup\$
    – Bubu
    Sep 24, 2022 at 5:31
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    \$\begingroup\$ @Bubu The difference is balance. If we're concerned about ground, we're either talking normal-mode signals (one trace over GND), or the common mode of a differential pair. It works when carefully constructed, as the symmetrical wires of a cable -- but when you have numerous signals on a PCB, all sharing one massive ground, there isn't really a meaningful way to obtain symmetry while also taking the difference between every single possible pairing of signals! LVDS style differential signaling is the response to that, and does indeed work very well, given that CM range is not violated. \$\endgroup\$ Sep 24, 2022 at 16:43
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    \$\begingroup\$ Again, balance: are we still talking single ended CMOS signals here? Just routing a signal parallel to a ground trace, doesn't do much: you're making a diff pair with one side driven, the other side shorted to GND, so the common mode impedance and voltage are all out of whack. If both traces are driven, complementary (one the inversion of the other, at ~no delay), that may be better. But it should still be done at lower signal levels (use resistor dividers?), for which an LVDS receiver will be needed. \$\endgroup\$ Sep 24, 2022 at 18:11
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    \$\begingroup\$ And again, since the signal rate is low, how about some jellybean comparators e.g. MCP6562 (well.. not that they're available either)? But really, single ended with generous source termination will handle commercial EMC just fine. \$\endgroup\$ Sep 24, 2022 at 18:15

First of all, consider whether it is possible to slow down the edges, e.g. with series resistors near the source. This will reduce cross-talk and the demands on the power distribution network (PDN). 200 MHz translate to rise-times of about 1-2 ns. Often times you get away with much slower rise-times.

But long story short: Any scenario with a solid ground plane and dielectric as thin as practical to keep fringing fields minimal should be the preferred way to go. Maybe you can use a 1 mm thick PCB instead of the standard 1.6 mm. This should already help a little.

The problem with having the return path adjacent to the signal on the same layer is that this is edge coupling only. So the fields tend to spread much wider than in the ground plane scenario (depends on the actual dimensions, of course).

PCB design is always a trade-off between MANY considerations. So it's hard to give definite answers.


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