I attempted to design my own H-bridge (P-MOSFET high-side), using a comparator hooked to a one-shot to limit current, modeled after the one-shot current-limited schematic described here.

enter image description here

Upon applying power (VINP is nominally 12 V), the circuit immediately failed. Both low-side MOSFETs failed, observed as less than 1 Ω resistance between all pins in the low-side MOSFETs and ground, whether or not gate current is applied.

I don't understand the failure. The MOSFETs seemed to fail immediately even before gate charge was applied. I don't think the voltage has ever exceeded 16 V, let alone the rated 20 V.

I'm thinking my next step is to replace the low-side MOSFETs with higher-voltage-rated ones, but it doesn't make sense to me why these failed. Is there some other culprit I'm missing?

enter image description here

  • 2
    \$\begingroup\$ What drives BRAKE_BRIDGE1/2? Show layout? Replace parts and try again with lower supply voltage, or with slowly ramping supply? (i.e. hook it up to the power supply, unplugged, then turn it on) Note that the PMOS will turn off EXTREMELY slowly with the mere 10k pullup (approx 50µs). \$\endgroup\$ Sep 24, 2022 at 4:41
  • \$\begingroup\$ @TimWilliams Yea, that's a lot in switching losses. The P-channel should really have an inverting gate driver. \$\endgroup\$ Sep 24, 2022 at 4:51
  • \$\begingroup\$ @TimWilliams Driving with an STM32. Thanks for advice on the slow off \$\endgroup\$ Sep 26, 2022 at 3:54

1 Answer 1


Based on the information in the question, here are the things I immediately see wrong or concerning.

  1. The lowside MOSFET is only rated for 20V and I would strongly recommend going higher. You can use 30V, but if you're just beginning I would go with 40-60V ratings of the MOSFETs. Although your 12V bus may not ever appear to rise very high, you will likely see very fast voltage over shoots across the MOSFETs during a switching transition. The spikes will likely be in the nanoseconds, but can still cause the device to fail.
  2. You have DC link capacitors (C15, C20, C24). This is good, but I would also recommend adding a couple of ceramic decoupling capacitors on the VINP to GND and place them very close to the drain of Q8 and Q22. I would look for something in the range of 10 to 22 uF.
  3. I personally wouldn't recommend driving the MOSFETs this way. I generally use gate drivers when controlling MOSFETs that have more than a few amperes going through them. As long as it's not constantly switching on and off, you should be okay though.
  4. There should be a gate resistor located close to each MOSFET. This helps control the speed at which the MOSFET turns on and off as well as reduce voltage overshoots and ringing on the gate. For something like this, I would recommend anywhere from 10 to 100 Ω to start out with. When you turn off a MOSFET that has current flowing through the drain to source, you will see a voltage spike due to parasitics. This is what the decoupling diode helps with. In your case, the low side MOSFET will turn on and off very quickly and would likely cause a voltage spike and ringing on the gate. The high side will turn off very slowly and will turn on very fast.

Since you are also driving the MOSFET with a logic IC, there will be a large current draw for a very short period of time while it's charging the gate. This is another reason why gate drivers are used is because they can handle driving amperes. This IC is likely only capable of driving in the milliamps range. The gate resistors will also help protect the logic ICs from overcurrent on the output. 5. R10 and R5 are really high values. I would recommend reducing this to something like 470 Ω to 1 kΩ. The lower resistance you go, the more power that resistor will dissipate. I generally use N-channels on high and low side, but that requires specific ways to drive them that I won't get into. Driving it a different way allows you to turn the device on and off faster without having a giant resistor that's going to get hot.

  1. There doesn't appear to be any dead time implemented. This is a period of time where the high and low side switch are both off during a transition. If you don't have any dead time, you will likely have "shoot through" which is when the high and low side (for example Q8 and Q15) are on at the same time. This will destroy the MOSFETs and sometimes the PCB. I won't explain too much more on dead time, but you need to research and understand what this is. In your case, as Q8 is turning off, it will turn off very slowly. At the same time Q15 turns on really fast and will be fully on while Q8 is still in the process of turning off. You will get a dead short and fry the board.
  2. Before installing the MOSFETs, verify your gate signals are correct on an oscilloscope. Make sure the waveforms look correct, and that there is dead time present between the high and low side MOSFETs. I would recommend using a variable power supply that's isolated and "inject" a voltage across the current sense to simulate the over current operation.
  3. Once you're ready to power on, I would remove at least the 560 uF capacitor and use a current limited variable power supply to power the board. This will help save you from failing boards left and right. Set the current limit on the supply to a reasonable range to what the system would normally draw. If something bad happens, you'll see the power supply go in to constant current mode. The reason I suggest removing the 560 uF capacitor is because if there is a problem, that capacitor will discharge very fast with a very high current. The MOSFETs may not be able to handle that discharge energy.
  4. Once everything appears operational, I would put the 560 uF back in and start measuring across the drain to source of the MOSFETs. Look for what the voltage spikes are during the switching transitions and make sure they don't exceed the voltage rating of the MOSFET.
  5. Another very important part is the PCB layout. If not done correctly, this will introduce a lot of parasitics which can cause high frequency ringing and voltage spikes.
  • 1
    \$\begingroup\$ +1:During the power turn on ramp, VinP should be delayed until the drive circuit’s power has stabilized. \$\endgroup\$
    – RussellH
    Sep 24, 2022 at 14:12

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.