Using a latch vs an AND gate to reduce switching activity in a low power VLSI design

Here is a problem that pops in low power design interview questions. The solution is the second picture down.

Why not use AND gates in place of the D-Latch? The person who created the solution did not go into this topic at all.

• This is a well documented topic. AND gates causes glitches in clock line, it can violate pulse width rule on clock as well. D latch is the classic solution to above two problems. Sep 26, 2022 at 4:47
• @MituRaj, the question is not about clock gating. The question is about data gating. Basically the data is being zeroed. Sep 27, 2022 at 0:59

Think about what would happen if half of the bits in the inputs were logic 1 most of the time. Using an AND gate would force those to become 0 when the other AND input is 0, so these bits would toggle on every cycle of your circuit and you would actually increase the power consumption due to switching.