I came through the following circuit in PIC microcontrollers datasheets, and I did not understand the highlighted statement:
If T1OSI pin is an input of a clock signal (square wave), and the inverter is off (open circuit), then T1OSO will generate the same signal through due to the resistor. And if the inverter is ON, T1OSO=NOT(T1OSI)+T1OSI which is not convenient (what did I miss in that)?
What do we mean by Power drain in T1OSC configuration?
When the inverter is on, it is "stronger" than the resistor, so there would always be current going through said resistor but T1OSC will be whatever output the inverter forces it at (think of the inverter as a very low resistance connected to the opposite voltage source).
This current going through the resistor, as well as the internal inverter circuitry, both cause a "power draw", this means that they consume energy over time. If you leave them on, a battery may last some amount of time. But turning them off means that they will not draw as much current (thus power, thus energy) and the battery will last longer. If this is not a battery powered application, you dont need to think about power draw.
Fun fact: by disabling some things you dont need at the moment in a microcontroller, it can go from draining/killing a battery in 3 days, to using that same battery for 15 whole years! Whenever you need the inverter, you turn it on, use it, turn it off and put the core to sleep.
If you are using the T1OSC or applying an external oscillator input then T1OSCEN must be set.
if it is not in use then those internal nodes will be floating and the inverter will be off so it is not biased mid-supply. Here, from the PIC16F88x datasheet you can see the logic:
When the T1OSCEN bit is set then the inverter is active and it will be biased via the resistor to mid supply so it will draw more current. If there is a crystal present it should start oscillating but the waveform will not be a square wave. An external clock will reduce that current because it will force the inverter to be high or low except when switching. Clearing T1OSCEN will disable the inverter/resistor (more than just disabling the output) and only leakage current will flow in that part of the circuit.
