What is the difference between always @* and always @(*) in Verilog-2001?
There are the same, but the better syntax is to use
always_comb in SystemVerilog.
It's better for synthesis because it has syntax restrictions for synthesis that will be caught during compilation of any tool, like a simulator. You won't have to wait until you try to synthesize and find out that your
always block is not combinatorial. It also is better at picking up sensitivities from function calls.
It's also better for simulation because always_comb guarantees that it will execute at time 0. That becomes critical when one of the signals on the sensitivity list turns out to be a constant and the other signals do not get initialized or have any events on them right away. For example
parameter en = 0; reg o1, o2; reg data;
always @(*) o1 = en & data; always_comb o2 = en & data;
o1 will remain 1'bx until data changes, whereas
o2 will go to 1'b0 at time 0.