What is the difference between always @* and always @(*) in Verilog-2001?
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2 Answers
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There is no difference, they mean exactly the same thing: infer my sensitivity list from the contents of the block.
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1\$\begingroup\$ Is one considered better practice? I've only ever come across the parenthesized version \$\endgroup\$– EricMar 28, 2013 at 15:50
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\$\begingroup\$ @Eric, it is up to the designer to choose whichever one he wants to use. There is no known bug or pitfall associated with either syntax. The parentheses are unnecessary if using an inferred sensitivity list. But if it causes confusion it is better just to use the parentheses as it causes no harm. \$\endgroup\$ Jul 17, 2013 at 1:51
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\$\begingroup\$ Here is a nice Verilog-2001 source: sutherland-hdl.com/online_verilog_ref_guide/… \$\endgroup\$ Jul 17, 2013 at 1:52
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There are the same, but the better syntax is to use always_comb in SystemVerilog.
It's better for synthesis because it has syntax restrictions for synthesis that will be caught during compilation of any tool, like a simulator. You won't have to wait until you try to synthesize and find out that your always block is not combinatorial. It also is better at picking up sensitivities from function calls.
It's also better for simulation because always_comb guarantees that it will execute at time 0. That becomes critical when one of the signals on the sensitivity list turns out to be a constant and the other signals do not get initialized or have any events on them right away. For example
parameter en = 0; reg o1, o2; reg data;
always @(*) o1 = en & data; always_comb o2 = en & data;
o1 will remain 1'bx until data changes, whereas o2 will go to 1'b0 at time 0.
