I am driving a P-MOSFET (IRLML6402) with ATtiny24A microcontroller. This is a battery powered system; that's why ATtiny is always on sleep. I originally configured a BJT which is driven by the microcontroller to pull P-MOSFET gate low when necessary, this requires pin to be driven high only when I want to turn on the system under P-MOSFET. But now I think of connecting ATtiny directly to P-MOSFET to keep the pin HIGH until I want the system to be on. System is 99.99% off that's why in this case, pin will always be high. Would keeping the pin always high cause power waste?

Also before putting the system to sleep, I must pull all pins to either low or high to reduce current consumption, which one should I do? It is easy to pull pins high by configuring them as input_pullup but I can also define them as outputs and set them "LOW" afterwards. I will reconfigure pins after waking up.

The question is asked for unused pins, used pins can't be configured as HIGH.


I have no pins floating already, details explained in comment. This is my code, no pins will be floating after configuring the pins as this once at startup:

DDRA |= (1<<LEDButtonPin) || (1<<AlarmPin) || (1<<FlashorPin) || (1<<PotEnablePin) || (1<<BuzzerPin); //Set "A" output pins
  PORTA &= ~((1<<LEDButtonPin) || (1<<AlarmPin) || (1<<FlashorPin) || (1<<PotEnablePin) || (1<<BuzzerPin)); // Set the outputs LOW
  DDRA &= ~((1 << ButtonPin) || (1<<pot_DEL_pin) || (1<<pot_DUR_pin)); // Set "A" input pins
  DDRB &= ~((1 << PIRPin) || (1 << PB0) || (1 << PB1) || (1 << PB3)); // Set "B" input pins
  PORTB |= (1 << PB0) || (1 << PB1) || (1 << PB3); // Set internal pullups for "B" pins
  • \$\begingroup\$ Here's a long blog post about all the things to do to reduce power in ATTiny link, which include reducing clock and so on. \$\endgroup\$
    – jonathanjo
    Sep 27, 2022 at 18:05
  • \$\begingroup\$ Can you draw an example schematic with the tool? \$\endgroup\$
    – Voltage Spike
    Sep 27, 2022 at 18:16
  • \$\begingroup\$ I added the schematic. Actually I don't have to do anything. I already configure the output pins (PA2, PA3, PA4,PA5,PA7) and pulled them low. I already set PB0, PB1, PB3 as "input pullup". I already have pulldown resistors for PA0,PA1 as potentiometers; for PA6 as R3. Finally there is PB2, which is grounded at the PIR sensor itself. So I think there is no pins floating. \$\endgroup\$ Sep 27, 2022 at 19:03

1 Answer 1


First and always, you need to find out yourself for the part you're using. You start by looking at the datasheet, then you look at your part in the schematic you've designed, then you test the finished article.

In general, though, for CMOS parts, for just the pin (not taking into account what it's attached to), there's no difference. MOSFET gates don't consume current when they're just sitting there, and unless you're using a more desktop-ish processor that has such small features that the transistors leak all the time, the power consumption of a GPIO pin with nothing attached is essentially zero.

  • \$\begingroup\$ Does having just voltage high on a GPIO pin without current may mean 1 μA power consumption? This is assuming some MOSFET inside leaks. Is a GPIO low voltage may mean 1nA or so current?. \$\endgroup\$
    – Amit M
    Sep 27, 2022 at 18:27
  • 1
    \$\begingroup\$ @AmitM a CMOS pair is going to have a pFET and an nFET. If they have similar oxides, chances are they'll have similar leakage, and one will leak in the high state while the other will leak in the low state. However, both leakages are tiny (e.g. one part I used has max 1 μA, typ 50 nA). The datasheet for the device you chose should indicate leakage currents. \$\endgroup\$
    – nanofarad
    Sep 27, 2022 at 18:48
  • \$\begingroup\$ Gate-to-Source Forward Leakage is -100nA according to datasheet. Does that mean there is a leakage from source to gate instead of gate to source? Source is potentially higher so that makes sense. There is no mention of gate to drain leakage in the datasheet. If I take the unmentioned gate-drain leakage zero and considering the resistance of Attiny output pin is too much to let any current flow in, can I say current consumption doesn't exists at all if I connect directly to MOSFET? \$\endgroup\$ Sep 27, 2022 at 19:18
  • \$\begingroup\$ I looked at IRFZ44N datasheet, it has a gate-source leakage of 0.04uA typical. probably there is unwritten gate-drain leakage in IRLML6402 (it is a PMOS that's why it is gate to drain). It's my choice to ignore or consider the very little current waste. \$\endgroup\$ Sep 27, 2022 at 19:27

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