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I'm using Libero SOC for the first time. I've used Quartus and Vivado before. I notice in the tutorials ways to use the graphical "Smart Design" file type as a top level module. But I can't for the life of me figure out how to set the top level module in the design to a verilog file, like I would with the Intel and Xilinx tools. Can anyone explain how to set an HDL file as the top level module in Microchip Libero?

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Answering my own question here, you need to make sure your HDL top-level compiles (I had a syntax error). Then if you click "Build Hierarchy", the HDL file will appear in the "Work" tab of the Design Hierarchy. You can then right click it and "Set As Root".

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