I'm using Libero SOC for the first time. I've used Quartus and Vivado before. I notice in the tutorials ways to use the graphical "Smart Design" file type as a top level module. But I can't for the life of me figure out how to set the top level module in the design to a verilog file, like I would with the Intel and Xilinx tools. Can anyone explain how to set an HDL file as the top level module in Microchip Libero?