I'm trying to figure out how a charge can be stored between two CMOS inverters and two more transistors.
I understand how the inverter works, just with a NMOS and PMOS base connected to a common input signal. But how is the data stored in the two MOSFETs that form the bistable elements between the inverters?
Although the MOSFET transistors are basically MOS capacitors with plates made of the gate electrode and the channel, it is neither a productive line of thought nor helpful to think of SRAM cell operation in terms of accumulated charge, as one can do with DRAM cells.
Instead, try and understand what the bistable element is and how it operates. The CMOS inverter is not just a two-transistor device with an NMOS and PMOS base connected to a common input signal (notice also that there is no base electrodes in MOSFETs, it is the GATE electrode that controls the transistor current). What is important for the logic device application, in the bistable circuit the load of an inverter is the high-resistance input of the other inverter, and the inverter works as an amplifier with a very high gain (>>1) in the middle range of gate voltages (\$V_{GND} < V_{G} < V_{DD}\$). Notice also that, as \$V_{G}\$ approaches \$V_{GND}\$ or \$V_{DD}\$, the inverter-as-amplifier's gain diminishes to zero.
Let \$V_{GND}=0V\$ and \$V_{DD}=2.0V\$. If you draw voltage transfer curves of the two invertors in this circuit in such a way that the input (output) of one inverter is shown along the X(Y) axis while the input (output) of the other inverter, along the Y(X) axis, you see (by inspection) that there are three equilibrium points, where the curves intersect one another. It is the points {0V, 2.0V}, {2.0V, 0V}, and approx. {1.0V, 1.0V}. For real inverters, the latter point not necessarily lies in the middle of the supply voltage range, but the other two equilibrium points are always very close to {\$V_{SS}, \, V_{DD}\$} and {\$V_{DD}, \, V_{SS}\$}.
Even small deviation of the gate voltage (due to thermal noises, for example) from the point {1.0V, 1.0V} causes the voltages at the inverter connection nodes to rapidly (because the gain is high) grow to/drop to \$V_{GND}, \, V_{DD}\$ or \$V_{DD}, \, V_{GND}\$, Therefore, it is the point of unstable (or metastable) equilibrium.
Now, if one inverter input is zero (\$V_{GND}\$), then its output, which is also the other inverter input, is logic one (\$V_{DD}\$), and vice versa. The two states, one with \$V_{GND}, \, V_{DD}\$ and another with \$V_{DD}, \, V_{GND}\$ voltages at the inverter connection nodes, are stable, because the inverter's gain at \$V_{G} = V_{GND}, \, V_{G} = V_{DD}\$ is zero and small variations of the output voltages do not amplify by the opposite inverter. For this reason, this circuit is known as a bistable element.
To enjoy full understanding of the bistable element operation, simulate the device made of MOSFET transistors in a simulator of your choice (the online simulator used on this site will do) and examine the voltage transfer characteristics.
To fully understand the SRAM cell operation, you also need to learn about read/write operations and functions of bitline/wordline wires.
If you want to think about this as storing a charge, then it's a minuscule charge in the connection between the inverters that is constantly being refreshed by the inverters. If you manage to flip the charge through the external connection, then the inverters will constantly refresh the new state.
