How is a bistable element formed with two inverters and two transistors in a 6T SRAM cell?

I'm trying to figure out how a charge can be stored between two CMOS inverters and two more transistors.

I understand how the inverter works, just with a NMOS and PMOS base connected to a common input signal. But how is the data stored in the two MOSFETs that form the bistable elements between the inverters?

Although the MOSFET transistors are basically MOS capacitors with plates made of the gate electrode and the channel, it is neither a productive line of thought nor helpful to think of SRAM cell operation in terms of accumulated charge, as one can do with DRAM cells.

Instead, try and understand what the bistable element is and how it operates. The CMOS inverter is not just a two-transistor device with an NMOS and PMOS base connected to a common input signal (notice also that there is no base electrodes in MOSFETs, it is the GATE electrode that controls the transistor current). What is important for the logic device application, in the bistable circuit the load of an inverter is the high-resistance input of the other inverter, and the inverter works as an amplifier with a very high gain (>>1) in the middle range of gate voltages ($$\V_{GND} < V_{G} < V_{DD}\$$). Notice also that, as $$\V_{G}\$$ approaches $$\V_{GND}\$$ or $$\V_{DD}\$$, the inverter-as-amplifier's gain diminishes to zero.

Let $$\V_{GND}=0V\$$ and $$\V_{DD}=2.0V\$$. If you draw voltage transfer curves of the two invertors in this circuit in such a way that the input (output) of one inverter is shown along the X(Y) axis while the input (output) of the other inverter, along the Y(X) axis, you see (by inspection) that there are three equilibrium points, where the curves intersect one another. It is the points {0V, 2.0V}, {2.0V, 0V}, and approx. {1.0V, 1.0V}. For real inverters, the latter point not necessarily lies in the middle of the supply voltage range, but the other two equilibrium points are always very close to {$$\V_{SS}, \, V_{DD}\$$} and {$$\V_{DD}, \, V_{SS}\$$}.

Even small deviation of the gate voltage (due to thermal noises, for example) from the point {1.0V, 1.0V} causes the voltages at the inverter connection nodes to rapidly (because the gain is high) grow to/drop to $$\V_{GND}, \, V_{DD}\$$ or $$\V_{DD}, \, V_{GND}\$$, Therefore, it is the point of unstable (or metastable) equilibrium.

Now, if one inverter input is zero ($$\V_{GND}\$$), then its output, which is also the other inverter input, is logic one ($$\V_{DD}\$$), and vice versa. The two states, one with $$\V_{GND}, \, V_{DD}\$$ and another with $$\V_{DD}, \, V_{GND}\$$ voltages at the inverter connection nodes, are stable, because the inverter's gain at $$\V_{G} = V_{GND}, \, V_{G} = V_{DD}\$$ is zero and small variations of the output voltages do not amplify by the opposite inverter. For this reason, this circuit is known as a bistable element.

To enjoy full understanding of the bistable element operation, simulate the device made of MOSFET transistors in a simulator of your choice (the online simulator used on this site will do) and examine the voltage transfer characteristics.

To fully understand the SRAM cell operation, you also need to learn about read/write operations and functions of bitline/wordline wires.

• I don't think there's anything wrong with thinking of an SRAM cell in terms of stored charge, if one views it as a pair of charge-based memory cells with circuitry which, if one bucket is full and the other is empty, will constantly try to top off the full bucket and drain the empty one. While most logic gates are designed to add or remove charge as quickly as possible, the gates are designed merely to overcome unwanted leakage into or out of the buckets while providing minimal interference with operations that would fill or empty the cells on a selected memory row. Commented Oct 2, 2022 at 15:18
• Would you please indicate a sample project of SRAM cell where the designer benefits from measuring charges held by MOSFET's Ciss Coss in litres and output currents in litre per sec? And what is the bucket's analogy for capacitance? Commented Oct 3, 2022 at 3:59
• In a "buckets" analogy, voltage is represented by the altitude of a water surface, capacitance is the horizontal cross-sectional area, charge is volume of water, and current is flow rate. Resistance doesn't have a good physical analogue since changes in flow rate with respect to pressure for a typical pipe won't be nearly as linear as the change in current with respect to voltage in most resistive materials, but otherwise an abstraction using open-topped reservoirs connected via pipes that are below them will properly model the relationship among voltage, charge, current, and capacitance. Commented Oct 3, 2022 at 16:48
• In any case, my point is that saying that a NAND gate will sink current from its output any time both inputs are high and the output isn't low is more accurate than saying that the output of a NAND gate is low whenever both inputs are high. Feedback-based memory circuits need to have a some means of creating non-zero delay at certain points the feedback paths. Otherwise, if delays in undesired places exceed delays in desired places, a memory circuit may be unable to reliably hold information when switching from write mode to idle mode. Commented Oct 3, 2022 at 16:55

If you want to think about this as storing a charge, then it's a minuscule charge in the connection between the inverters that is constantly being refreshed by the inverters. If you manage to flip the charge through the external connection, then the inverters will constantly refresh the new state.

• How are the wordline and bitlines manipulated to write or read from the element? Commented Oct 2, 2022 at 4:25
• When you address the element via the wordline, you get the current state on the bitlines, and when you drive the bitlines to override the inverters, the cell will take on the new state. Commented Oct 2, 2022 at 4:31
• So then the bitlines are bidirectional and differential? Commented Oct 2, 2022 at 4:33
• Bidirectional, yes. Differential, somewhat. You would only ever drive them in opposite directions, but they are not evaluated in the receiver by comparison. Commented Oct 2, 2022 at 4:35
• A resource I found mentions it more like the side of VCC and Ground switching back and forth between the on and off stages. Is this more accurate, and if so, how is this difference held and refreshed? Commented Oct 2, 2022 at 5:22