Which should I use? I'd like to use it to model circuits for homework and to possibly reuse parts circuits in other designs.
\$\begingroup\$
\$\endgroup\$
6
-
\$\begingroup\$ Huh? I have no idea what is being asked here. \$\endgroup\$– Olin LathropCommented Mar 29, 2013 at 13:10
-
3\$\begingroup\$ Question is clear and makes sense if you've seen the tool. It might be a bit too localized, mainly professionals can afford these tools. Don't know how many schools offer access to it - probably not many. \$\endgroup\$– user16324Commented Mar 29, 2013 at 16:18
-
2\$\begingroup\$ @OlinLathrop Sounds like a question you cant write an answer to. \$\endgroup\$– KortukCommented Mar 29, 2013 at 18:55
-
\$\begingroup\$ @Kortuk: A little more context in the question would have been a good idea explaining what this is about. Relying on the title in the body of the question is also not a good idea. These two together just made the question seem like gobbledygook. Judging from the 2 close votes, I was not the only one that thought so. This is precisely the risk you run when you don't even give enough context for those that don't know anything about the specific thing you are asking about to be able to recognize that. \$\endgroup\$– Olin LathropCommented Mar 29, 2013 at 21:37
-
1\$\begingroup\$ @OlinLathrop It seems like a very niche question that you would really have to know to be of great help. \$\endgroup\$– KortukCommented Mar 30, 2013 at 2:04
|
Show 1 more comment
1 Answer
\$\begingroup\$
\$\endgroup\$
1
re: (fair question but now deleted) in comments : HDL Designer is a professional tool for logic design from Mentor Graphics. It has been around for a while, originally under the Renoir name, it's only been HDL Designer for about six or seven years.
It intends to add higher levels of abstraction over VHDL and Verilog designs. From what I have seen of Verilog, it might be useful there, but if you're using VHDL you can write at a higher level of abstraction without it, and using HDL Designer badly can keep your VHDL code stuck in the dark ages...
However, that said :
a Library, like a VHDL library, is for things (types, components, packages, utilities) that you will re-use in different places, either within a single project or common to multiple projects.
A Project is what you would use to structure a single design, e.g. for a single FPGA, the testbench for it, and possibly the board it is on.
One reasonable use of HDL Designer is to create wrappers for substantial VHDL components (CPU, memory, bus interface, FFT processor etc) and to create structural VHDL designs using them, in the form of HDL Designer block diagrams. That way you effectively have compilable documentation...
-
\$\begingroup\$ Thanks Brian! It seems that it's almost impossible to find good documentation or examples with Mentor Graphics, and the whole way it structures projects/libraries, combined with my university's complicated setup that corrupts my projects if I use two different versions of MG, causes a lot of issues. \$\endgroup\$ Commented Mar 31, 2013 at 4:14