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In the presented flip-flop, suppose the Enable signal is high, the S is low, and R is high. Now we set the Preset low (0) and the Clear high (1). In this condition, we expect Q=1 and Q'=0.

But checking the circuit gives us contradictory outputs. Because the Preset is low, the output of the upper NAND gate would be 1 and therefore Q=1. Since the R is high, the R* would be low (0) and therefore the output of the downside NAND gate would be also 1 or we can say Q^=1. That means both Q and Q' need to be high which is not possible. enter image description here

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  • \$\begingroup\$ What do you mean by "should not work" this way? It works how it works; if it doesn't work the way you want it to work then change the design. \$\endgroup\$ Oct 4, 2022 at 19:19
  • \$\begingroup\$ Q and Q' being high at the same time is possible. It's just not allowed if you want to use it as a flip-flop. \$\endgroup\$ Oct 4, 2022 at 20:39

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By holding both the /Preset input Low and R input High you are forcing the flip-flop into an unstable (illegal) state.

When you change either of those inputs, the flip-flop will change to a legal state.

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It means both Q and Q-complement need to be high which is not possible.

This is not a good point of view and analysis.
For analyzing this circuit, one should say first ... that the 2 outputs are labelled Q1 and Q2 ... and that if some conditions are met, Q1 & Q2 could be complementary states.

One must do a "complete" analysis before saying there is a "problem".
Note that for such analysis, it is very important to check all the delays associated with each gate, because behavior can be "different" ...

Check my post at this link for the R-S FF with NAND gates.

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In my opinion, the circuit is ok, preset Signal Signal take over the clock and S input cause Q is 1, Q' is 0, and CLEAR SIGNAL take over or bypasses the clock and reset Signal, cause Q goes to 0 and the Q' goes to zero.

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