Updated again: it's a very interesting idea, but I'd checked carefully the CRC and ECC functionality of the card in all its various modes; might be considered weak against future versions of the standard. Confirmed in comments (thanks @jpa) that CRCs are bitwise per databus line, which makes it sound promising.
I believe there
will could might be a difficulty because of the CRC values transmitted over the data bus. The CRC over data is CCITT16 (x16 + x12 + x5 + 1)
Further reading the JESD84-A43 standard, it appears that one CRC is calculated per data line, in which case the argument against is invalid, see below.
10.2: For data blocks one CRC per transferred block, per data line, is generated
in 4 bit and 8 bit bus configurations, the
CRC16 is calculated for each line separately.
If the CRC on data bus D n is calculated on the data bits n, then the data bus bits are effectively independent columns, and the shuffle should be undetectable.
My reading of the 8-bit and 4-bit modes says that if you never wanted to use 4-bit mode, you could shuffle any of bits 1-7 with any other.
If anything calculates across the byte it would fail:
Suppose you swap bits 2 and 1 in hardware
rot(x) := swap bits 2 and 1
crc16(0x32) = 0x1611
crc16(rot(0x32)) = crc16(0x34) == 0x76d7
rot(0x16) != 0x76
so the CRC would fail if it's done across the byte
Calculated with crccalc.com and pycrc16, xmodem variant.
If the eMMC device doesn't do anything except calculate and transmit the CRC, it might be possible to calculate and send something which reverses the effects of the data bus shuffle. It might also be possible to ignore the CRC, such as in stream mode.
The same kind of issue might affect the BCH (542,512) error correcting code, if used.
Here's the portion of the JEDEC doc saying the CRC is transmitted on the data lines. The drawing makes it look like the CRC is 16 bits / 4 bits / 2 bit according to the bus width of 1 / 4 / 8 bits. But closer reading suggests it is always 16 bits long.
JESD84-A43 standard (link at NXP)
Digression The firm I worked at in the 1980s built an error-correcting circuit. In order to shuffle the bits around to minimise noise hitting bits from the same error-correction block, we put in an area of RAM which was connected to the CPU through two sets of address and data latches; one normal, one bit-reversed so A0:A15 mapped to A15:A0 and D0:D11 mapped to D11:D0. Thankfully all ROMs were connected the ordinary way around.