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I have coded a Verilog module with the following initial conditions:

initial begin
    cnt     = 8'd0;
    cs      = 1;
end

I was wondering, after a successful synthesis, if the initial begin/end statement can be synthesized. I'm saying it because Vivado (Artix 7 FPGA) didn't point to any error/warning.

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2 Answers 2

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Yes, initial values for reg are supported in Artix (and the majority of other) FPGAs. Opinions differ on whether it's a good idea to rely on it; there are some subtle gotchas that may or may not apply to you; see the linked thread for more information.

Note that you can't initialize a wire, you can only assign it. This is how Verilog works and has nothing to do with support or lack thereof in a particular FPGA family.

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Do not use initial values in synthesizable HDL i.e. HDL which creates a logic circuit in your target FPGA/CPLD/ASIC. Use a reset term, controlled by the reset input you have.

This makes your design far more portable other devices and lets you drop in other IP more easily. In my experience, the vast majority of IP you'll encounter uses reset terms, for the same reason of portability.

In a RAM-based FPGA, initial values are typically added into the configuration file during synthesis and therefore loaded into the relevant registers during device configuration. This is not true of flash-based FPGAs or many CPLDs, as well as ASICs, so the same design put into these devices now won't work and the source can be hard to track down.

This is explained further in this answer. It covers VHDL but the point is the same.

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  • \$\begingroup\$ I think a blanket "do not use" statement is not helpful. Portability is an issue in the cases you mentioned and there are other gotchas, but it doesn't make a design not portable, it just restricts the portability somewhat, and this may be acceptable in many designs. (I am not the downvoter.) \$\endgroup\$
    – TypeIA
    Oct 12, 2022 at 16:45
  • \$\begingroup\$ @TypeIA, I obviously disagree, for all the reasons stated. The effort to make it portable is no more as the effort to make it not. There's no worthwhile up-side to designing non-portable firmware, which is expanded on through the link. Hence a "don't" rather than an "avoid". I've done a couple of dozen FPGAs and CPLDs, very large and very small, and found it's worked very well for all that. (Never thought you were, by the way :-) ) \$\endgroup\$
    – TonyM
    Oct 12, 2022 at 16:52

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