I am designing a device where 100 slaves are connected to a master with SPI bus and the bus must be isolated on each node. Speed requirement is 1 MHz and cables are fairly short (about 10 cm between each slave, 10 meters total).

Plan is to to add fairly powerful line drivers to master and just drive 100 optocouplers connected to same wire in parallel. 20 mA for each is 2 A total.

I am wondering how much if any the total 2 A current affects the propagation delay at the end of the cable? Do I need to (or should I) for example add schmitt triggers to every node and supply the isolated Vdd for them with separate thicker wires, then drive the optos with schmitt triggers locally on each slave, to reduce the load on high speed cables?

Answers to comments:

I calculated the propagation delay thru 10 m of copper cable using the speed 0.65 c, result 51.3 ns which should be more than fine with 1 MHz.

Then the propagation delay of opto which is 75 ns and propagation delay of line driver circuit at the master card which depends but can be less than 50 ns anyway. This gives me total of 175 ns.

When the slave receives the clock with 175 ns latency and outputs the MISO bit the latency to another way is less because no high current led driver is needed so it's 75 ns in opto and 51 ns in cable. Total roundtrip 175 + 126 ns...? But there must be more in this like the inductance and capacitance of the load? Those I don't quite understand.

BTW this would be mSPI not SPI, meaning there is only one common CS line and master sends the slave address as first byte. Not that it would matter the actual bus characterics.

More thoughts:

After thinking more about this I think adding schmitt triggers or any kind of input triggers to slaves only makes the situation worse as they tend to have much higher input capacitance than optos and propagation delay of theyre own?

The driver side at the master card could be a N MOSFET with high speed gate driver like MIC44F18. MOSFET drives the paraller connected opto cathodes, anodes connected to any suitable DC voltage. Capacitance of optos is very low, 0.6 pF with those I checked, shouldn't be a problem.

What i don't quite understand is how the inductance of the wire affects the 1 MHz signal with ~2 A current? Current travelling in the wire is of course reduced after each opto, this makes situation easier?

So because of the optos basically this is a high speed led driver more than traditional SPI bus.

More thoughts vol. 2:

This is not going to work as I planned. I may or may not be able to do the MOSI and CLK with high current mosfet driver and optos, but how about the MISO line.

For obvious reason I need to be very conservative about the cost of slave card and not so much about the cost of master card, as there are 100 slaves per master.

Option 1: Add several spi buses, each bus reduces both the length of the cable and the required speed as there are less slaves to poll. 2 spi buses means 5 m of cable and 500 kHz. 4 SPI buses means 2.5 m of cable and 250 kHz.

How many buses are needed to achieve 10 kHz per slave?

And how would you do the isolated MISO line? Logic level open collector isolators are much faster and stronger per buck than transistor output, but requires isolated vdd and gnd wires from the master. Strong pull-up resistor must be added to the master, current output of opto 50 mA so with 5 V 300 Ω maybe? Would that do with 2.5 m and 250 kHz?

How about the wiring of tx lines. Can I use shared wire for anodes of MOSI, CLK and CS (i.e. connect them at slave PCB) or is it better to use paired cable and pair per line and connect at master PCB?

Option 2: Add differential driver to MOSI line and do TX lines with MOSFET and optos...?

Like this: https://www.digikey.com/en/products/detail/texas-instruments/DSLVDS1001DBVT/10448345

$0.75 per slave. But it still requires isolator between slave MCU and LVDS driver and wires for isolated vdd. Expensive compared to several SPI buses which only requires additional parts to master card.

More thoughts to option 1:

I think I need to use push-pull output opto or add totem pole transistor circuit to each slave after the open collector opto. Pull-up after the long wire would be problematic...

Or maybe I can add extra opto to the master card in MISO line and drive that with open collector optos in each slave? That would add extra propagation delay but it's small enough with 500 kHz and could use cheaper and faster OC optos on each slave without extra transistors.

When driving a LED I don't have to care about the voltage and pull-ups only the current matters.

Would that work? Need to draw a diagram of this approach.

enter image description here

How about RS-422?

Okay you got me thinking this one which i dropped at the begin for being too expensive, without even checking the prices carefully. But does it really cost that much more.


1/1 Transceiver Full RS422, RS485 8-SOIC. $1.19 / 100pcs

It saves me two optos per slave. https://www.digikey.com/en/products/detail/liteon/6N137S/ Those being $0.35 each makes it $0.7 total. So RS422 + two optos costs $0.5 * 100 = $50 more than four optos and banging the anodes.

But it only needs two pairs of wire plus the power lines and overall is much cleaner and less error prone approach.

I still need to be able to sync all the slaves within 0.5us but i think can do that over RS-422 wires as well by first sending a message which puts the slaves to a special sync mode and internally (in mcu) disconnects the RX pin from the UART and use it as regular input pin.

All of those RS-422 tranceivers needs plenty of juice as they need to drive the optos so need a strong power cables. But those can be branched to keep relatively short and i need to bring the master vdd to slaves anyway even with spi opto cathode driver circuit thing to allow slave to transmit.

Also one RS-422 bus should be enough, should easily get 1Mbps with it i think. 🤔


Hmm... "Maximum devices 10 (1 driver and 10 receivers)" https://en.wikipedia.org/wiki/RS-422

One driver can only drive 10 receivers? That is a limitation i didn't know about. It would mean i need 10 drivers to master card. Can i connect all of them in paraller to same UART? :) Different bus side cables of course, 10 slaves per driver.

  • 2
    \$\begingroup\$ Have you calculated how far out of sync the furthest slave response will be (as seen at the master) compared to the local master clock? \$\endgroup\$
    – Andy aka
    Oct 16, 2022 at 10:42
  • \$\begingroup\$ You may not able to use a clock speed of 1 MHz with 100 slaves. You may have to scale it down to less than 100 KHz. \$\endgroup\$
    – Amit M
    Oct 16, 2022 at 10:50
  • \$\begingroup\$ Perhaps you should open up what you are doing, instead of trying to ask how to solve it by opto-isolating 100 SPI devices. With the cost of power supply and electricity capable of providing multiple amps to just drive few hundred optos, you could solve the actual problem. \$\endgroup\$
    – Justme
    Oct 17, 2022 at 11:13
  • 1
    \$\begingroup\$ Agree, an X-Y problem. Question is [initially] about Y, a proposed but likely unworkable solution to X; ask about X instead. \$\endgroup\$ Oct 17, 2022 at 11:51
  • \$\begingroup\$ Does it have to be parallel, could it be serial (doubly so) instead? That is, chain the nodes, if they need to be isolated from each other so be it, but it's only one isolator per node. Clock in a few hundred bits, then latch it in. Some SPI devices can do this, and the discrete solution is simply shift registers (74HC164 and 595). Mind propagation delay to MISO, it will have to be reclocked after that many nodes. \$\endgroup\$ Oct 17, 2022 at 11:53

1 Answer 1


It's not the current load that is a concern, but SPI can't generally drive 10 m of cable. Rise/fall times and noise will corrupt your data.

If you put the optocouplers at the master, then each opto needs to drive 10 m of cable -- won't work. If at each slave, then the slave has to drive the wires -- still won't work. In addition signal reflections at each end of the cable (it acts as a transmission line, not a single lumped inductance) will be problematic and cause multiple transitions and data corruption. Typically these are eliminated with termination resistors; most SPI I/O's cannot drive such a low impedance (~ 100 Ω).

  • \$\begingroup\$ I agree with this. At that long distance, inducatance and resistance of the wire comes into play and there may be reflections. SPI is not good for lengths greater than 10m. There may be some delay between MISO signal at 100th slave and clock signals of SPI master as Andy_aka said. Clock speed has to be reduced to less than few tens of KHz. \$\endgroup\$
    – Amit M
    Oct 16, 2022 at 17:33
  • \$\begingroup\$ When you say SPI can't drive you mean the SPI port of the mcu? The SPI is only driving the high speed gate driver ic which is on the master card, gate driver then drives the gate of large enough nmosfet which drives the current to the cathodes of the optos. Optos must be on slave cards as slave cards operates at different ground levels. \$\endgroup\$ Oct 16, 2022 at 19:30
  • \$\begingroup\$ I am not trying to do ttl level spi bus with 100 slaves. Idea is to drive the optos (leds) with the sufficient current and voltage. \$\endgroup\$ Oct 16, 2022 at 19:44
  • \$\begingroup\$ Can the current of the reflections be high enough to affect the optos? I understant that they can mess up the high impedance transmission line but each opto requires several mA to activate. 100Ω terminal resistor at the end of the line is not a problem when driving with mosfet. \$\endgroup\$ Oct 16, 2022 at 19:50
  • \$\begingroup\$ You need to explain (diagram) where the long wires are -- at the Tx end or the Rx ends ? \$\endgroup\$
    – jp314
    Oct 16, 2022 at 20:50

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