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DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The trade-off is tighter Tr/Tf, skew, and jitter timing requirements on the data lines (bringing them in line with the clock's timing requirements), and some added complexity in the drivers/receivers.

QDR clearly does not have the same property: the transition rate of the data lines is twice that of the clock, so the max Tr/Tf must inherently be shortened, which means the design bandwidth goes up and the timing requirements on the data lines get even tighter. Driver and receiver complexity also go up again, with four clock phases needing to be synthesised.

From what I could find online, one of the first devices to implement QDR was an Intel CPU (I believe the P4?), which apparently used QDR as a way to "bodge" twice the interprocessor data rate onto a shared FSB clock. The justification for this is clear - the FSB clock couldn't be doubled because it was also used by other devices, but when two processors had ownership of the bus they could signal however they liked, so QDR allowed them to improve the throughput. This makes some amount of sense.

GDDR5X also implemented QDR. I couldn't get hold of a copy of the GDDR5X specification (it's paywalled) but the QDR feature is mentioned in this memory product datasheet. What I don't understand is why they chose to utilise QDR in this case. The signal integrity requirements should be the same as if the DDR bus clock was doubled. It's a fully integrated stack in terms of standardisation, so there's no third party interop to consider, unless they expected GDDR5 and GDDR5X memory devices to be present on the same bus (which seems extremely weird). As far as I'm aware the only two devices on the GDDR5X bus would've been the DRAM ICs and the GPU's memory controller.

As far as I can tell, the idea didn't stick around and QDR wasn't included in later memory standards.

What am I missing? Why did GDDR5X implement QDR instead of simply doubling the DDR bus clock?

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  • \$\begingroup\$ Running the data clock at a multiple of some base clock (2, 4, ,8...) is common, usually because a parallel data stream is being muxed into a narrower bus. In this case the module is made of a bunch of slower dram arrays which are muxed onto a faster bus. \$\endgroup\$ Commented Oct 18, 2022 at 17:06
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    \$\begingroup\$ I'm not talking about clock multipliers, I'm talking about the use of QDR signalling specifically, which is a separate matter. Each DRAM IC is receiving the QDR signal, it isn't being muxed. \$\endgroup\$
    – Polynomial
    Commented Oct 18, 2022 at 17:09
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    \$\begingroup\$ @user1850479 the question is why not just use the 4x clock as the main clock \$\endgroup\$ Commented Oct 18, 2022 at 19:51
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    \$\begingroup\$ @user1850479 everything but the data pins would be... the clock pin.? Why multiply by 4 to clock the data pins, instead of dividing by 4 to clock the DRAM? \$\endgroup\$ Commented Oct 18, 2022 at 20:55
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    \$\begingroup\$ @user1850479 The question is then: given that the data lines are already transitioning at a higher bandwidth on the bus, why bother using QDR to have the clock transition half as frequently again, when with DDR you could have the exact same symbol rate on the data lines and you don't need the more complex driver & receiver. \$\endgroup\$
    – Polynomial
    Commented Oct 18, 2022 at 21:15

1 Answer 1

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I'll try a stab an overall answer that addresses both the original question and some of the additional ones in the comments.

From what I could find online, one of the first devices to implement QDR was an Intel CPU (I believe the P4?), which apparently used QDR as a way to "bodge" twice the interprocessor data rate onto a shared FSB clock. The justification for this is clear - the FSB clock couldn't be doubled because it was also used by other devices, but when two processors had ownership of the bus they could signal however they liked, so QDR allowed them to improve the throughput. This makes some amount of sense.

First, let's be clear that this is a much more common technique than just the Pentium 4. LVDS for example is 30 years old and works similarly do your GDDR memory:

https://en.wikipedia.org/wiki/Low-voltage_differential_signaling#/media/File:FPD_Link_I_serializer_example.png

Compare to your GDDR datasheet:

datasheet image

Looking at the red box, this is essentially the same thing as the old LVDS system, except the PLL multiplies only 4:1 instead of 7:1 in that example and the inputs are DRAM arrays. But aside from that, they do essentially the same thing, mux 4/7 slower devices into one individual channel running at 4/7 times the speed. The reason all of these different systems use this approach is that it works pretty well when you want to serialize a bunch of slower devices onto a faster bus.

What I don't understand is why they chose to utilise QDR in this case. The signal integrity requirements should be the same as if the DDR bus clock was doubled. It's a fully integrated stack in terms of standardisation, so there's no third party interop to consider, unless they expected GDDR5 and GDDR5X memory devices to be present on the same bus (which seems extremely weird). As far as I'm aware the only two devices on the GDDR5X bus would've been the DRAM ICs and the GPU's memory controller.

Reading through the comments, what you are really asking is not why did they choose QDR specifically, but rather why do they choose to multiply up the clock where it is needed rather than multiply it up elsewhere and then send the high frequency everywhere it is needed from a central location. The problem with that is that sending very high frequency signals long distances is hard and uses a lot of power, so you try not to do it if you don't need to. At the same time, at 12 GHz the differential receivers are complex devices that run hot and are expensive to integrate, so if you don't need one, you probably don't want to pay for one, both in power and money. Since there isn't any advantage to sending the higher frequency, instead you send the slower clock and avoid all of that cost.

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  • \$\begingroup\$ Your answer doesn't make any sense to me, and I think you're still misunderstanding the question. Imagine data line transmits a constant repeating sequence of "01010101", forever, with no line coding or any other fanciness. In a simple synchronous serial transmission where data is sampled on the rising edge of the clock only, a single symbol period is the length of one clock cycle. One clock cycle contains two transitions (rising edge, falling edge) and one symbol period contains one data line transition. With DDR, there are two symbol periods per bus clock cycle, so two data line transitions. \$\endgroup\$
    – Polynomial
    Commented Oct 20, 2022 at 13:33
  • \$\begingroup\$ So, with DDR, you get a matched "maximum" number of transitions in a single bus clock period, with the clock line transitioning twice and the data line transitioning 0-2 times depending on the data (but always two in our repeating 0101... pattern example). The symbol period and the clock's inter-transition period are made the same. This makes the timing and slew rate requirements exactly the same between the data lines and the clock line. The line drivers can be exactly the same and the power consumption required to meet the timing requirements is identical for both clock and data. \$\endgroup\$
    – Polynomial
    Commented Oct 20, 2022 at 13:40
  • \$\begingroup\$ If you visualise the DDR example with a repeating pattern, the clock and data lines look identical - they're both square waves same frequency. When we move to QDR, you double the symbol rate again. Critically, the bus clock frequency itself has not changed - in GDDR5X the bus clock remains at 3GHz in both DDR and QDR modes, with DDR achieving 6GBd and QDR achieving 12GBd. Now, if you visualise the QDR example with the repeating data pattern, you've got two square waves: a clock signal at 3GHz, and a data signal at 6GHz! \$\endgroup\$
    – Polynomial
    Commented Oct 20, 2022 at 13:51
  • \$\begingroup\$ In the actual GDDR5X QDR implementation this is exactly what happens with WCK and DQn: WCK runs at 3GHz, and the DQ lines run at 12GBd. The command and addressing lines run on a separate (in terms of rate) clock domain that does not change behaviour between DDR and QDR modes, so that portion of the bus is irrelevant for this discussion. Since power consumption in the line drivers is proportional to slew rate, and there are 32 data lines, the majority of the power increase comes from running those DQ lines at 12GBd (6GHz square wave with repeating pattern data). \$\endgroup\$
    – Polynomial
    Commented Oct 20, 2022 at 14:02
  • \$\begingroup\$ This is where my question arises: given that QDR mode already has 32 differential data line drivers and receivers with electrical properties equivalent to a 6GHz clock driver (a hard requirement due to the number of transitions per second that may occur on each data line!), and we already have to design around those timing/skew constraints, why not just double the WCK frequency from 3GHz to 6GHz and continue to operate in DDR mode to achieve 12GBd? The aggregate power consumption for the bus would go up by 3% at most, and in return you reduce the complexity of the system. \$\endgroup\$
    – Polynomial
    Commented Oct 20, 2022 at 14:12

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