DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The trade-off is tighter Tr/Tf, skew, and jitter timing requirements on the data lines (bringing them in line with the clock's timing requirements), and some added complexity in the drivers/receivers.
QDR clearly does not have the same property: the transition rate of the data lines is twice that of the clock, so the max Tr/Tf must inherently be shortened, which means the design bandwidth goes up and the timing requirements on the data lines get even tighter. Driver and receiver complexity also go up again, with four clock phases needing to be synthesised.
From what I could find online, one of the first devices to implement QDR was an Intel CPU (I believe the P4?), which apparently used QDR as a way to "bodge" twice the interprocessor data rate onto a shared FSB clock. The justification for this is clear - the FSB clock couldn't be doubled because it was also used by other devices, but when two processors had ownership of the bus they could signal however they liked, so QDR allowed them to improve the throughput. This makes some amount of sense.
GDDR5X also implemented QDR. I couldn't get hold of a copy of the GDDR5X specification (it's paywalled) but the QDR feature is mentioned in this memory product datasheet. What I don't understand is why they chose to utilise QDR in this case. The signal integrity requirements should be the same as if the DDR bus clock was doubled. It's a fully integrated stack in terms of standardisation, so there's no third party interop to consider, unless they expected GDDR5 and GDDR5X memory devices to be present on the same bus (which seems extremely weird). As far as I'm aware the only two devices on the GDDR5X bus would've been the DRAM ICs and the GPU's memory controller.
As far as I can tell, the idea didn't stick around and QDR wasn't included in later memory standards.
What am I missing? Why did GDDR5X implement QDR instead of simply doubling the DDR bus clock?