# Unwanted DC offset at the input of inverting op-amp

I'm designing an envelope generator for a sort of mini synthesizer I'm currently working on. I want the envelope signal to evolve (rise or decay, depending on the SPDT switch) only when the switch (SW1) is closed. The first part of the circuit (RV1, C1, R1 and D1) handles the rising envelope signal. The first op-amp ensures that the capacitor discharges only when the switch is open (through D1 and R1) and buffers the signal. That signal is then inverted to generate the decay envelope signal. The problem is that, when the switch is open, the output of the first op-amp, which should be very close to ground (typically 5mV according to LM324 datasheet), is at about 600mV. It surely can't be an impedance problem, the output impedance of the buffer is very low and the input impedance of the inverting amp is 10k. However, if I swap R2 and R3 for 100k resistors, the offset is minimized (I get about 60mV instead of 600mV). Why does this happen? Does it have to do with the inverting amplifier being biased at 2.5V?

Edit: LM324 power supply voltages are 0V and 9V (9V single supply).

• When you measure 600mV at the output, what do you measure at the input? Commented Oct 19, 2022 at 23:29
• And the power supply voltages to the are what, 0V and 5V? Commented Oct 19, 2022 at 23:59
• You'll probably have better luck with a true rail-to-rail opamp that can operate at 5V. Commented Oct 20, 2022 at 0:49
• It is possible that the 2.5 V bias on U2B will cause its output to be 5V and this will cause a 250 uA current into the output of U1A. This might be enough to cause a 600 mV offset on its output. Commented Oct 20, 2022 at 1:36
• @brhans At the input of the buffer (U1A) I measure almost exactly 0V (1-2mV). Commented Oct 20, 2022 at 21:18