I have 2 capacitors.

The first one is 100 nF and the other one is 1 μF.

When doing the layout, which capacitor should be placed close to the IC power pin and why?

I have seen in many places that the smaller capacitor (100 nF) is placed close to the IC pin.

Why is that good practice and what is the reason behind it?

  • \$\begingroup\$ Does this assist? resources.altium.com/p/… \$\endgroup\$
    – Kartman
    Oct 20, 2022 at 8:29
  • \$\begingroup\$ So, the article suggests, which I also learnt right? Lower value capacitor should be placed close to the IC pin? Right? \$\endgroup\$
    – user220456
    Oct 20, 2022 at 8:41
  • \$\begingroup\$ Does not must be lower capacitance value but lower ESR. 0.1mkF is just tradition, it was biggest ceramic. \$\endgroup\$
    – user263983
    Oct 20, 2022 at 9:48
  • 1
    \$\begingroup\$ Lower impedance, not just ESR! \$\endgroup\$
    – Polynomial
    Oct 20, 2022 at 10:00
  • \$\begingroup\$ This is somewhat unrelated but may prove illuminating: electronics.stackexchange.com/questions/638344/… \$\endgroup\$ Oct 20, 2022 at 17:08

4 Answers 4


The black art of decoupling.

The reason you put decoupling capacitors close to the required IC is to supply current for the high frequency signals. This means you want to reduce the inductive loop between the current source (the capacitor) and the IC.

There are two ways to reduce inductive loop: reduce distance or increase track width. Increasing track width is usually impractical, and then the pin of the IC is of a defined width you cannot change. So you want the decoupler capacitors to be as close to the IC as possible.

But then then capacitor case has an impact. The smaller the physical size of the capacitor, the smaller the inductive loop, the better decoupling performance you’ll get for a defined capacitance.

Higher capacitance can store more current to allow for high signal spikes. However larger capacitance often means larger case size, larger inductive loop, reducing performance.

Which brings us to your question: which cap to put closer to the IC. You want to put the smaller case capacitor closer to the IC to make the most of smaller inductive loop. Which is why you’d put the smaller capacitor value closer to the IC, as they (as a general rule) are in smaller cases.

It is possible to run the maths, comparing frequency performance of capacitance value against case size, the graphs are quite interesting. A quick internet search will probably find you good ones.

  • 1
    \$\begingroup\$ Thank you for the answer. Suppose, I've 2 capacitors of which both are 0402 sizes. First one is 100nF and the other one is 1uF. Still, it would be better performance to put the 100nF close to the IC pin and the 1uF behind the 100nF? Am I right> \$\endgroup\$
    – user220456
    Oct 20, 2022 at 8:52
  • 3
    \$\begingroup\$ In a word: Yes. Using more than one word: probably, but if you run the frequency numbers you'll see that the 100nF isn't doing anything the 1uF isn't also doing, so there is an argument to have 2x1uF caps would be better \$\endgroup\$
    – Puffafish
    Oct 20, 2022 at 9:04
  • \$\begingroup\$ Thank you. So, just to clarify : So, its the case size of the capacitor thats important and not the value? \$\endgroup\$
    – user220456
    Oct 20, 2022 at 9:07
  • 1
    \$\begingroup\$ It's both. A 1uF can provide a lot more current for higher powers, a 100nF can probably come in a smaller case for higher frequencies. \$\endgroup\$
    – Puffafish
    Oct 20, 2022 at 9:19
  • 2
    \$\begingroup\$ @Puffafish Beware of capacitance change with applied voltage on ceramic capacitors. It is likely a 1uF 0402 will use X5R dielectric and have a lower voltage rating than the 100nF capacitor which is probably a X7R dielectric and higher voltage rating. The X5R capacitance will change significantly with applied voltage, perhaps less than half of the expected capacitance. \$\endgroup\$
    – qrk
    Oct 20, 2022 at 23:36

Typically, high frequency currents are lower power than lower frequency currents.

Another tendency is that smaller capacitances have lower parasitic inductance whether it be because of the way the capacitor works or simply because it is in a smaller package.

These two tendencies mean that what limits the high frequency decoupling capability of a capacitor is its parasitic inductance, not it's capacitance value. And that the limiting factor in decoupling low frequencies tends to be the capacitance value rather than the parasitic inductance. This is because high frequencies tend to be low power and do not need much charge for decoupling but the parasitic inductance needs to be low enough that the high frequency current can actually pass through the capacitor to begin with. And low frequencies aren't as affected by the parasitic inductance so can pass through the capacitor easily but are high power and so need more charge capacity for effective decoupling.

Since higher frequencies are more sensitive to trace inductance (more voltage drop for the same current at the same frequency), it means that the capacitor you are using to decoupling high frequencies must minimize trace inductance between the capacitor and its load. This tends to be the smaller capacitance and so the smaller capacitance must be closest to the load to minimize trace loop area. The capacitor for low frequency decoupling is less sensitive to trace inductance and so can be placed farther away, and this tends to be larger capacitor.

In a perfect world where a larger capacitor has the same parasitic inductance as a smaller capacitor, you would use just the larger capacitor since it has low enough parasitic inductance to decouple high frequencies while also having enough capacitance to decoupling higher energy frequencies (which tend to be low frequencies). Sometimes this is the case where you have two different capacitances of the same technology that also come the same package which can largely determine the parasitic inductance. In that case you might just go with the larger capacitance and omit the smaller one.

If you need to decouple high frequencies that carry a lot of energy, then things get hairy.

Also, paralleling decoupling caps of different values has its pitfalls. Each capacitor has parasitics that can form RLC tank circuits of different values that resonate with each other and amplify noise frequencies causing more problems than if they were not there. This is called "anti-resonance peaking" if you want to look it up. That's why you ideally want all your parallel capacitors to be of the same type and value so all the RLC tank circuits are the same. This can be impractical though since it may require too many small capacitors to end up with the required bulk capacitance to decouple the higher energy low frequency signals. So there is tradeoff.


Long story short: Generally you want the capacitors with the lowest high frequency impedance having the least loop inductance to the supply pins of the chip. That's because you don't want to degrade the high frequency performance of such a capacitor by connecting it with a large loop inductance.

Important to note here is that the high frequency impedance of a capacitor is dominated by its physical size and not its nominal capacitance. In other words: You want the smallest physical size capacitors having the least loop inductance to the supply pins of the chip. Often times that just happens to be the one with the smallest nominal capacitance.

But with MLCCs, for example, your 1 uF and 100 nF could be the same physical package size. So they might have similar high frequency impedance. In this case it doesn't really matter which of them is connected with the lowest loop inductance. The reasoning for choosing two different values might be questionable in the first place.

And if you have closely spaced power planes near the surface the chip is mounted on, the actual location of the capacitors might not even matter too much. Connecting the capacitors and the pins of the chip with via pairs directly to the power planes might yield lower total loop inductance than any connection with surface traces.

  • 1
    \$\begingroup\$ With regards to your 3rd paragraph, if they have similar high frequency characteristics you can just omit the 100nF since the main reason it's there is for the better high frequency response that the larger capacitance lacks, but if the larger capacitor can handle it then you don't need the smaller one. \$\endgroup\$
    – DKNguyen
    Oct 20, 2022 at 16:53
  • \$\begingroup\$ But it's not a given that equal package size == equal or even similar high frequency impedance. It plays a role only. \$\endgroup\$
    – TypeIA
    Oct 20, 2022 at 17:49

Short answer:

  • Smaller, lower inductance caps go closer to the pins. They’re most effective there; placing them farther away adds routing inductance and defeats their purpose.

  • Take care when mixing values to avoid anti-resonance. This can cause cases where your decoupling is worse than the values by themselves. Using 10x multipliers is a good rule of thumb (so your 0.1uF + 1uF should be ok); simulate it to be sure (quick and easy, try k-sim here.) Personally I like using 2.2uF MLCC with 0.1uF for under-chip bypass.

  • Consider alternative cap types like reverse-aspect, feed-through, etc. Their higher performance in the 1 ~ 10uF range can reduce the number of caps you need.

Rather than give a further long-winded explanation, I’ll refer you to this Murata doc: https://www.murata.com/-/media/webrenewal/support/library/catalog/products/emc/emifil/c39e.ashx


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