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I have a system that detects pulses amplitudes with a peak detector, the signal from which is then digitized with an ADC. Pulses can sometimes overlap, so I've decided to "zero" the peak detector input when ADC conversion is in progress (there can be sometimes multiple ADC conversions which are averaged afterwards). The problem is with the schematic before the peak detector.

schematic

simulate this circuit – Schematic created using CircuitLab

My idea was to short the input signal to ground with R1 and Q1. However, the problem is that a small positive impulse and a large negative impulse are present when the transistor base switches (see scope picture: top graph is base voltage, middle graph is the collector voltage, bottom one is the input signal from a buffer). The positive impulse is very short and does not concern me: first of all, C1 just reduces it a bit, and, secondly, the peak detector does not even react to it (it's too short). The negative impulse, however, concerns me very much since the registered amplitude is reduced when the next input pulse comes when negative voltage is present on the transistor collector, and deadtime is therefore significantly increased .

2SC9017, normal forward active, from top to bottom: base, collector, input

However, I once accidentally inserted the transistor in wrong orientation and swapped collector and emitter. For some reason, the schematic works a bit better in this mode, though the negative impulse is still present. I've also tried other NPN bipolar transistors (2n3904, BC547, 2n5551, KT368A); some behave a bit better, some a bit worse, but the general idea is the same: they all work better when connected in reverse active mode.

2SC9018, reverse active, from top to bottom: base, collector, input

My questions are:

  1. Why does this negative pulse happen? I do understand the cause for the positive pulse (collector-base capacitance most probably), but the negative impulse is way too long for that and timing is a bit off.
  2. How to combat this negative "bump"?
  3. Why in reverse-active mode this schematic works better? Is it just due to lower beta?

P.S. Yes, I've tried mosfets: the positive pulse from them is way higher and does influence the peak detector, and the negative pulse is also present (about the same voltage as a bipolar transistor in reverse-active mode)

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  • \$\begingroup\$ I don't see the small positive impulse. Where does it occur? \$\endgroup\$
    – Andy aka
    Commented Oct 20, 2022 at 12:38
  • \$\begingroup\$ @Andyaka it's more visible on the second picture (the capacitor does smooth it off very well) - right before the signal drops to ground and when the base voltage rises rapidly. \$\endgroup\$
    – sx107
    Commented Oct 20, 2022 at 13:20
  • \$\begingroup\$ Possible parasitic "miller" capacitance of the transistor? And lead/trace inductance. Did you try a low-gate-capacitance MOSFET, like the 2N7000 series? \$\endgroup\$
    – rdtsc
    Commented Oct 20, 2022 at 13:26
  • \$\begingroup\$ Scales are needed i.e. how big can the pulse be and how low might it be? Oscilloscope time base numbers would also help. \$\endgroup\$
    – Andy aka
    Commented Oct 20, 2022 at 13:44
  • \$\begingroup\$ @Andyaka both of these are present on the photos : all vertical scales 500mV/grid, all horizontal - 1uS per grid line \$\endgroup\$
    – sx107
    Commented Oct 20, 2022 at 17:34

1 Answer 1

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Interesting, it seems charge injection includes reverse recovery (storage).

Usually BJTs are used under bias (significant collector current), where the collector voltage stays near Vce(sat) until charge is cleared. Charge is essentially the B-E junction undergoing reverse recovery, and the transistor remains conductive until that charge is dissipated. Dissipation occurs both through base current directly (recombination) and charge drawn out from the base pin (which, with 100Ω to a CMOS pin pulling down, will be noticeable). When charge is clear, Ic dominates, and Vce pulls up smoothly.

Since you're discharging approximately zero current, the first change would be to vastly reduce base current. You're overcharging the B-E junction relative to what's needed on C. This will also go somewhat slower (capacitance will dominate instead), so there is a tradeoff.

Evidently, with essentially zero Ic, the charge persists in the B-C junction too (there's no current or voltage to clear charge from that region quickly, as there is during normal switching), and it gets yanked significantly negative when B-E turns off first.

The reason, then, that inverted operation seems better is, more or less, the lower hFE of that configuration. You're injecting relatively less excess charge, so there's less to recover, and less offset as a result. (Charge emission tracks with doping concentration, and the de facto emitter is normally highly doped to improve hFE, while the collector is lightly doped to increase breakdown voltage. Swapping them around means a lightly-doped emitter that leaves less excess charge.)

And because capacitance will dominate once the excess charge is reduced -- the fact that jellybean MOSFETs aren't available with capacitances nearly as low as BJTs, means you will indeed see more charge injection with them. You won't see the lumpy waveform, it will have a smoother capacitive curve, but it will be significant for this reason. (Example: compare 2N3904's ~4pF with 2N7000's ~30pF. An RF MOSFET would do fine, but these are long obsolete, aside from very high frequency types which wouldn't really be desirable here.)

I suggest using an analog switch, which balances charge injection using a complementary MOS structure. CD4066 might not be fast enough for your purpose but there are 74HC equivalents, and other families for signal switching including up to quite high bandwidth.

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    \$\begingroup\$ Thank you very much, got it! Exactly as I thought. By the way, I'm a bit of an idiot: if you look closely, the signal is a tad bit negative when the transistor closes, and the signal after the transistor matches it perfectly in reverse-biased schematic; so, the reverse-active transistor in this schematic works perfectly. \$\endgroup\$
    – sx107
    Commented Oct 20, 2022 at 17:47
  • \$\begingroup\$ @sx107 Good point! \$\endgroup\$ Commented Oct 20, 2022 at 20:05

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