module lab3(input [9:0] SW, input [3:0] KEY,
output [6:0] HEX0, output [6:0] HEX1, output [6:0] HEX2,
output [6:0] HEX3, output [6:0] HEX4, output [6:0] HEX5,
output [9:0] LEDR);
wire clk = ~KEY[0]; // this is your clock
wire rst_n = KEY[3]; // this is your reset; your reset should be synchronous and active-low
wire [3:0] state_in;
reg [3:0] b;
assign state_in = state;
// moore component
module moore(input [3:0] SW,
input clk,
input rst_n,
output reg [3:0] state);
endmodule: moore
// combinational component
module combinational(input [3:0] SW, input [3:0] state_in,
output [6:0] HEX0, output [6:0] HEX1, output [6:0] HEX2,
output [6:0] HEX3, output [6:0] HEX4, output [6:0] HEX5);
endmodule: combinational
endmodule: lab3
My intention is to connect the output reg 'state' from the 'moore' module to the input of the 'combination' module. (reg 'state' in this case is meant to act as a flip flop).
I know that a reg can drive a wire using an 'assign' statement, which is what I tried above. The file compiles when the placeholder reg 'b' is used to drive the wire, but when I try to connect it to the output reg 'state' from the 'moore' module, it doesn't compile. I'm struggling to understand why this is the case since I'm new to Verilog.