I executed the following code on vcs:
module test;
reg v,y,a,b,p,m;
initial
begin
v = 1'b0;
#5 y = 1'b1;
fork
#20 a = v;
#15 b = y;
join
#40 v = 1'b1;
fork
#10 p = v;
begin
#10 a = y;
#30 b = v;
end
#5 m = y;
join
end
initial
$monitor($time, "\n v=%b y=%b a=%b b=%b m=%b p=%b \n",v,y,a,b,m,p);
endmodule
The console gives the following output:
Compiler version S-2021.09; Runtime version S-2021.09; Oct 24 03:00 2022
0
v=0 y=x a=x b=x m=x p=x
5
v=0 y=1 a=x b=x m=x p=x
20
v=0 y=1 a=x b=1 m=x p=x
25
v=0 y=1 a=0 b=1 m=x p=x
65
v=1 y=1 a=0 b=1 m=x p=x
70
v=1 y=1 a=0 b=1 m=1 p=x
75
v=1 y=1 a=1 b=1 m=1 p=1
What's the significance of using the 'begin and end' statements in the second fork
block?