SEMIKRON: Effect of gate inductance on Eon (Switching losses)

Question

I was reading the AN1403 "Determining Switching Losses of SEMIKRON IGBT modules" from SEMIKRON.

https://www.semikron.com/service-support/downloads/detail/semikron-application-note-determining-switching-losses-of-semikron-igbt-modules-en-2014-08-19-rev-00.html

And I came across the following lines talking about the effect of the gate inductance on the Eon Switching losses:

Here is the circuit (Figure 7)

Here are their measures:

If I correctly understand, it is said that the higher the inductance is, the lower the Eon would be, where Eon are the energy loss for turning on the IGBT.

Well, from my mind, a higher inductance will limit the rise of the gate to source voltage, and it will slow down the commutation of the IGBT and so the losses would be higher.

I am not sur to understand what SEMIKRON is saying: "The effect of this inductance can be compared with a current source, which supplies additional gate charge at the beginning of the "Vge-plateau" period."

I think that as at the beginning of the turn on process the current is maximal and limited by the driver, the inductor is magnetically charged and when the miller plateau arises, the inductance is still a bit charged and so the inductance tends to reduce in time the Miller plateau. But clearly, I do not think that it is as simple as it.

Do you understand why a higher inductance on the gate reduces the Eon?

Thank you for your help.

---------------------------------E D I T ----------------------------------- I have done a simulation for trying to understand what SEMIKRON is saying, and the result of the simulation is not showing the SEMIKRON's measures.

Here is the simulation circuit :

Then I added to the circuit different inductances :

And here are the results showing the gate voltage and the power losses :

And here are the power losses :

I integrate it and the simulation with the higher inductance is the worse in term of Eon.

Answer 1

Remember that turning "on" the gate requires charge.

If there were no inductance on the gate signal, the gate would initially appear as a capacitor, and the gate charge rate would be determined by the gate voltage until the Vge plateau period, which occurs when the gate voltage reaches the gate voltage threshold. This plateau occurs when the reverse transfer capacitance (a capacitance between the collector and the gate) starts to affect the charging rate. As the collector voltage goes rapidly negative, this collector-to-gate capacitance tends to drive the gate voltage more negative, so the gate voltage and charging current is reduced (or sometimes reversed if the gate drive impedance is high enough.) This is the cause of the "Vge plateau." During a switch, the negative feedback effect of this phenomenon causes the gate voltage to rise until switching starts, then remain at a more or less constant level while the collector voltage drops, then rises again. Hence the "plateau."

The introduction of the inductance on the gate input has a tendency to counteract this. While the external inductance causes a longer delay to reach the threshold voltage, when the threshold voltage is reached, the gate charging current flowing in the inductor has a tendency to remain constant, regardless of the drive voltage. You can see this occurring in Vce in figure 10: with the lower inductance, Vce starts to switch 40ns sooner, but with the higher inductance the plateau effect on Vce is less pronounced. The "current source" contribution adds to the charging from Vge voltage, making Vge appear lower when measured from drive before the inductive, external traces.

Since the device switching time is reduced, Eon is also reduced - in the same manner that it would be if a higher-voltage, higher current gate driver were used. It's not clear to me why this is presented in this way, unless just to demonstrate the potential effects of parasitic inductance on the switching and reverse recovery.