# Single-ended follower with zero quiescent current?

Reading The Art of Electronics (3rd edition), I came across the following sentences in section 2.4.1:

An npn emitter follower cannot sink current... . The result is that a single-ended follower operating between split supplies can drive a ground-returned load only if a high quiescent current is used.

I understand that "an npn emitter follower cannot sink current", but It isn't clear to me how it follows that "a single-ended follower operating between split supplies can drive a ground-returned load only if a high quiescent current is used".

In the following circuit the fact that the follower cannot sink current means that the input voltage must be larger than $$\-V\frac{R_L}{R_L+R_E} + 0.6\$$. By the way, it seems to me that here the quiescent current is zero (Q1 is off when there is no input signal).

simulate this circuit – Schematic created using CircuitLab

• Consider what the capacitor coupling means. What is the average current flowing through each capacitor? It has to be zero because the average current through every capacitor is zero. Current goes one way and then goes the other way. Now ask yourself: When the current goes from right to left through C2, which way does it go? Oct 24, 2022 at 22:15
• You can't connect a capacitor to the base of a transistor like that, there must be a dc path to ground provided.
– user173271
Oct 24, 2022 at 22:42
• apadana, Assuming for a moment that @James' comment is dealt with (by providing biasing), and you actually have an emitter follower using your example only as behavioral for now, then $R_{_\text{E}}$ must be on the order of, or less than, $R_{_\text{L}}$. And if so, then pretty much by definition the quiescent current must be very high. It's just not a good way to go. Sure, you can make it work and accept the incredible wasted heat, as a demo. But the only practical use is in an emergency or as a quick youtube demo.
– jonk
Oct 24, 2022 at 22:56
• When they say it "can't sink current" what is meant is that: if the transistor "wants" the output voltage to be "low", all it can do is turn off. In other words, it's up to the lowly R_E to do all the work. So, if the need is to sink a high current while maintaining a "low" output voltage, then R_E is going to be small. And if R_E is small, for the transistor to bring the output voltage "up", it's going to be required to pump a LOT of current thru R_E because of its smallness. So to bias the ckt at some "central" operating point, lots of quiescent current will need to be flowing. Oct 24, 2022 at 23:04
• electronics.stackexchange.com/questions/560681/…
– G36
Oct 25, 2022 at 3:29

The capacitors in your example make it difficult to explain what's going on, because they introduce a dynamic, time-dependent behaviour. In other words what happens next depends on what the state of the circuit was a second ago. When you use the term "quiescent", the assumption is that the circuit has settled into a static, steady state.

During quiescence C1 and C2 have charged to some constant potential difference, and no longer pass current. At that point, since no current is flowing through them, they could be removed, and not a single node in the circuit would change potential. Effectively, in the quiescent state everything on one side of a capacitor is electrically isolated from everything on its other side, until something somewhere changes.

For this reason, when talking about quiescence, any analysis or explanation must assume that capacitors are absent, or open-circuit. Due to C2, RL in your example doesn't exist from the transistor's or RE's perspective. Similarly C1 isolates everything to its right from the source of input signal, so Q1's base is effectively floating.

In your circuit during quiescence, therefore, no base current flows, so no emitter current flows, the voltage across RE is zero. The potential at the left side of C2 (Q1's emitter) is a steady -V volts, but the potential at the right side of C2 is zero, because C2 has charged to a constant potential difference of V volts.

C1 is problematic, because in quiescence it causes Q1 to completely switch off. For this reason it's unusual (at least, I've never seen it) to see an emitter follower's base AC coupled with a capacitor in this way. It only makes sense to explicitly set the potential of Q1's base, and never leave it undefined as C1 tends to do here.

Similarly, C2 "hides" the load, and its only when something changes that the effect of RL would become apparent. It is true that as your circuit stands, quiescent emitter current is zero, but that's only because the base is floating, with no base current flowing.

You use the term "no input signal" as if that's a normal condition. It isn't normal, because as I said before, the base would have some explicitly applied potential. Considering we are using split supplies, −V and +V, the quiescent base potential would likely be zero volts, smack in the middle. For instance, if this were an audio stage, presumably the input signal is a potential difference that fluctuates above and below an average of zero. In such a case you wouldn't choose a quiescent base potential anywhere near either supply rail, because any input excursion approaching -V volts or +V volts would result in clipping; rather you'd bias the base somehow to be zero volts on average.

Clearly, any base potential greater than $$\-V + 0.6\$$ will cause current to flow in RE, so if average base potential is zero volts, that's a significant quiescent current.

From the perspective of the output side, (by output I mean the emitter potential) since the base always has an explicit potential somewhere between −V and +V, the emitter is always 0.6V less than that. Again, if this average value is close to either supply rail, then clipping will occur if the the input were to swing close to or beyond the supply potentials. This is another reason why you would never allow the base to float, any why you would always make sure that the quiescent, average emitter potential is well within the supply extremes, to permit both positive and negative excursions without clipping.

Therefore the emitter potential is also, on average, somewhere well above −V volts, and current through RE is always non-zero.

You may well have an application using split supplies, for which the output is always at or near the negative supply potential, and only ever goes positive from there, in which case you could make the claim that "quiescent current is zero", but that's uncommon. Normally, average emitter potential is nowhere near the negative supply rail, and consequently emitter quiescent current is significant.

To address the problem of a ground-returned load, it's sufficient to see that if you've set the quiescent emitter potential to be −V, to obtain zero quiescent current through RE, then emitter voltage can never fall below that.

All C2 does is to copy the potential changes (the AC components) at the emitter over to RL, so whatever excursion constraints exist at the emitter also exist at the top of RL. In other words, if the emitter never falls below −V volts, the top of RL never falls below ground potential (not necessarily true at certain frequencies, but that's another story).

If C2 were not there, RL and RE form a potential divider between 0V (ground) and −V (the negative supply rail), and hopefully it's clear that RE would have to be much, much smaller than RL to ensure that RL "drops" as much of that output potential as possible. Since RE has to be small, and quiescent (average) output potential should be somewhere near 0V (not −V), you have no choice but to suffer large currents through RE even when the input signal amplitude is zero.

## Split vs single-ended supply

Let's dispose of something that may be getting in your way.

A quote from AofE, 3rd edition:

The result is that a single-ended follower operating between split supplies can drive a ground-returned load only if a high quiescent current is used.

I think you may be getting tripped up by their phrasing. (To be clear, I take their meaning of split to mean bipolar. As evidence, see Figure 2.26 on page 84.)

It actually doesn't matter if this stage used a bipolar or single supply. Assuming the capacitor is sufficiently large, the mean voltage difference across it automatically adjusts itself to the situation.

You can easily see this by first considering the DC case. Just remove the output capacitor. The now-opened end of the load, which has no current through it, will be at ground. The newly-unloaded emitter's output will be some DC value. The output capacitor, if added back, would charge up to this difference given sufficient time.

If you now apply a sufficiently high frequency AC (or use sufficiently large-valued input and output capacitances) so that capacitive impedances can be neglected (can be treated as a short for AC purposes) and if you've biased up the emitter follower stage sufficiently well that it can supply the load's current throughout the entire AC cycle (a full, 100% class-A output without clipping) then you will see the same (or similar) mean difference.

That's because motion through a full AC cycle doesn't change the average.

Again, assuming that the stage can support the entire AC cycle as a class-A output then different bias cases (bipolar vs single-ended supply rails) merely alter the average across the output capacitor. But the different circumstances do not change what the load sees, as the capacitor has already adjusted itself to the DC difference between the load and the stage's biasing point and the AC itself can't and won't alter it.

(The only niggling non-linear detail in the presence of an input signal would be that the voltage across the base-emitter junction will be varying with the logarithm of the class-A collector current and this will slightly alter the AC mean when compared with the DC difference.)

In short, don't get hung up on the fact that the authors chose to write split supplies when discussing the circuit. It's a red herring.

## Proper emitter-follower biasing

I want to focus on how you may bias this stage to properly drive a single-ended load.

But I may as well also keep the earlier point in sight.

So let's look at the two cases, one using a symmetrical split supply and the other using a single supply, while at the same time focusing on developing a proper bias for some specific load:

simulate this circuit – Schematic created using CircuitLab

To avoid having to take into account the input and output coupling capacitors, the following must be true:

• $$\X_{C_{_\text{IN}}}\ll R_1\,\vert\vert\, R_2\,\vert\vert\,\left[\left(\beta+1\right)R_{_\text{E}}\right]\$$ at the lowest frequency of interest.
• $$\X_{C_{_\text{OUT}}}\ll R_{_\text{L}}\$$ at the lowest frequency of interest.

As is often true in electronics, we mostly care about a range near $$\X\$$; namely, $$\\frac1{10}X \le X \le 10 X\$$. So the meaning of $$\\gg\$$ is anything more than $$\10X\$$ and the meaning of $$\\ll\$$ is anything less than $$\\frac1{10}X\$$.

This is because most of the interesting stuff happens in this range and so this concept provides a useful 1st-order approximation, when designing. (You can always later go still deeper, if there's a need to do so.)

The above rule also plays into properly designing this stage (regardless of bipolar or single supply rail(s)) to drive $$\R_{_\text{L}}\$$. Here, to do it right, we need $$\R_{_\text{E}}\ll R_{_\text{L}}\$$. If both $$\X_{C_{_\text{OUT}}}\ll R_{_\text{L}}\$$ and $$\R_{_\text{E}}\ll R_{_\text{L}}\$$ then the stage can properly drive $$\R_{_\text{L}}\$$.

So, let's start the proper design given $$\R_{_\text{L}}=8\:\Omega\$$ and a lowest frequency of interest (to keep the capacitor values semi-reasonable) of $$\f=1\:\text{kHz}\$$.

Suppose that the input source is $$\\pm 5\:\text{V}\$$ and that we want the output (at the emitter) to be at least $$\2\:\text{V}\$$ away from either rail. So this means we can set $$\V_{_\text{CC}}=+9\:\text{V}\$$, $$\V_{_\text{EE}}=-9\:\text{V}\$$, and $$\V_{_\text{POS}}=+18\:\text{V}\$$.

Now find $$\C_{_\text{OUT}}\ge 200\:\mu\text{F}\$$ and $$\R_{_\text{E}}\le 800\:\text{m}\Omega\$$. (We'll use stiff biasing so $$\C_{_\text{IN}}\approx\frac1{10} C_{_\text{OUT}}\$$ should be fine.)

Let's first consider the idea of setting the quiescent emitter voltage about halfway between the rails (in either of the above cases.) Here, find $$\I_{_\text{Q}}=\frac{V_{_\text{CC}}-V_{_\text{EE}}}{2\,\cdot\,R_{_\text{E}}}=\frac{V_{_\text{POS}}}{2\,\cdot\,R_{_\text{E}}}=11\frac14\:\text{A}\$$!

Wow! Time to step back and reconsider for a moment...

Let's now ask about what the load itself seems to require. For an input signal of $$\\pm 5\:\text{V}\$$, find that $$\\frac{5\:\text{V}_{_\text{PEAK}}}{\sqrt{2}}\approx 3.5\:\text{V}_{_\text{RMS}}\$$. This means $$\\frac{3.5\:\text{V}_{_\text{RMS}}}{8\:\Omega}\approx 440\:\text{I}_{_\text{RMS}}\$$. If $$\I_{_\text{Q}}\$$ is more than 10 times this, then we might consider that as okay.

So let's set $$\I_{_\text{Q}}=4.4\:\text{A}\$$ as sufficient. We can't change $$\R_{_\text{E}}\$$. But we can bias the operating point so that the emitter is about $$\800\:\text{m}\Omega\cdot 4.4\:\text{A} \approx +3.5\:\text{V}\$$ above the bottom rail.

We've no clue about the BJT's base-emitter voltage, except that this will be a big BJT! Let's select the OnSemi D44H11 and take a peek:

(Let's just call that $$\1\:\text{V}\$$.)

So, using a stiff biasing pair (again, that $$\10X\$$ comes into play), find (using standard values) that $$\R_1\approx 27\:\Omega\$$ and $$\R_2\approx 10\:\Omega\$$.

Here's the LTspice run for that, using both circuits:

Take note that the output looks reasonable and that there is no difference in what the load sees between these circuits. The mean voltage across the output capacitor will be different. But the output load cannot see that difference.

## Improper emitter-follower biasing

So, let's see what happens when you don't bias things well. Instead, let's violate the above rules and set $$\R_{_\text{E}}=80\:\Omega\$$. Rather than using $$\R_{_\text{E}}\approx \frac1{10}R_{_\text{L}}\$$, we are using $$\R_{_\text{E}}\approx 10 R_{_\text{L}}\$$ here -- the other end of that scale I mentioned earlier.

$$\R_{_\text{E}}\$$ is now 100 times larger than before and therefore $$\I_{_\text{Q}}\$$ is about 100 times smaller.

We'll also adjust the biasing pair, similarly, making the pair also 100 times larger in value. (I'll leave the capacitors alone, though.)

Note that once again the load sees the exact same thing, regardless of bipolar vs single supply. But the output no longer looks much like the input signal. Instead, most of the cycle is wiped out and only part of it looks about right.

The problem with this new stage design is that while the BJT can actively pull upward on the load through the output capacitor for part of the AC cycle, it cannot actively push downward on the load for the rest of it.

This use of the phrase pull upward is imprecise, though. You will find it commonly used, but it grossly simplifies what is really taking place.

So let's think carefully about the details. There's more nuance here that meets the overly simplistic eye.

1. The output capacitor has some average voltage across it at the start of each input signal cycle. We don't know what that average is and it may be either negative or positive, as we will see. But it adopts some value based upon the cycle-to-cycle behavior of the circuit.
2. As the input signal rises upward in the first $$\90^\circ\$$ of the signal's sine, the BJT's base rises and the emitter follows it, easily sourcing current into its load formed by the combination of $$\R_{_\text{L}}\$$ and $$\R_{_\text{E}}\$$. (The output capacitor's voltage difference must be increasing in the 'more positive' direction in order to supply $$\I_{R_{_\text{L}}}\$$, which acts to slightly hinder the voltage across the load. But with a large enough output capacitor value, this hindrance isn't significant.)
3. The input signal crosses through $$\90^\circ\$$ and starts downward. So long as $$\I_{R_{_\text{L}}}\$$ remains positive, the output capacitor remains a sink for the emitter's source of current and $$\R_{_\text{L}}\$$ can easily pull downward on the output capacitor. The BJT's emitter can still follow.
4. At some point $$\I_{R_{_\text{L}}}=0\:\text{A}\$$ and the BJT's emitter is now only sourcing current into $$\R_{_\text{E}}\$$, which is the only current sink remaining.
5. Just after, as the input signal continues downward and $$\R_{_\text{E}}\$$ continues to be the only sink available, $$\R_{_\text{E}}\$$ pulls just barely enough downward on the emitter end of the output capacitor such that $$\R_{_\text{L}}\$$ starts sourcing current into the emitter node. But because $$\R_{_\text{E}}\$$ is 10 times larger than $$\R_{_\text{L}}\$$, it doesn't take long before $$\R_{_\text{L}}\$$'s current swamps out what $$\R_{_\text{E}}\$$ can sink and at this point the BJT's emitter stops sourcing current and the BJT turns off.
6. Nothing more happens via the BJT until the input signal swings completely back around. In the meantime, the voltage drop across the load will be about a tenth of the voltage drop across the emitter resistor. (Not much, but slightly negative.) The emitter voltage will just sit there (almost) until the input signal gets back around and high enough that the base-emitter voltage goes positive and the emitter can return to sourcing current, again.

All the above complexity can be summarized, though. The emitter can actively pull upward but it cannot actively pull downward. This fact leaves the emitter resistor to passively pull downward. But because the emitter resistor is 10 times larger than the load, it cannot pull much and therefore most of the voltage drop occurs across the emitter resistor during this part of the cycle with only a small negative drop across the load.

Less than half the input cycle gets through. And if you further reduce the quiescent current of the emitter-follower stage, even less of the input cycle will appear at the output.

## Summary

If $$\R_{_\text{E}}=\frac1{10}R_{_\text{L}}\$$ then the output does a fair job of replicating the input, but because of the very high $$\I_{_\text{Q}}\$$ required it is also very wasteful to run this one-quadrant driver.

A solution is to add another active device to replace the passive emitter resistor.

Finally, note that the output capacitor charges up in just such a way (in all cases) that the bipolar and single supply stages "look exactly the same" from the point of view of the load.

There is no problem when the transistor's base swings positively, the emitter can provide all the current required for the increased voltage across RE and RL.

The problem comes when the transistor's base swings negatively. If RE is a fairly high value then the quiescent current is fairly low. As the base swings negatively, the voltage across RL increases negatively and the increased current through RL replaces some of the current through RE which was previously provided by the transistor's emitter.

When the negative going voltage across RL increases to a level where all the current flowing through RL is providing all the current being sunk by RE then the voltage across RL can increase no further and it limits (flattens off or saturates).

If RE is kept to a low value (high quiescent current) then the negative going voltage across RL can increase to a larger amplitude before saturating, that is to say before the current through RL is equal to the current through RE.

If the voltage at the base keeps reducing after the voltage across RL has saturated then Vbe will reduce or even turn negative.

Without a dc path to ground (no base biasing), the base current will slowly charge C1 and the voltage at the emitter will gradually reduce until it reaches the negative power rail.

When the same error is made with an op amp's input, the circuit can initially test out fine but later on it's found that the op amp's output very slowly drifts, over hours, towards one of the rails until it saturates as the input capacitor is slowly charged by the op amp's input bias current. It can be a difficult problem to find the cause when a circuit is designed without a input dc path to ground.

In summary, the quiescent emitter current through RE is the amount of current available to supply the load RL when the voltage across the load swings in a negative direction and so the maximum negative voltage across the load RL is limited to Ie(quiescent) * RL.

The dc voltage across C2 must be 0V. That means $$\V_{R_{E}}=V\$$ which will require a high quiescent current, especially if $$\R_{E}\$$ is small.

We will have to assume the base bias is there even though it is not shown.

... only if a high quiescent current is used.

The answer is "probably" no. Take a look at this picture.
NB: start of the transient is not so beautiful ... Only steady state is ok.