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I'm currently working on a capacitance model which will be part of a greater compact model for a planar RFET.
I use Sentaurus TCAD to generate capacitance data, which I use to understand the capacitance behaviour and to compare my model to. Looking at the capacitances in general and for simplification purposes using a MOSFET as a simple example the question arises how the capacitances are defined?
More concretly two sub-questions arise:

  1. Where does the capacitance lie? Can you think about the capacitance like a plate capacitor sitting between the terminals? If yes, what capacitance is \$C(g,g)\$ describing?
  2. Why are capacitances negative? Does it mean that the capacitance is really negative, or does this phenomena arise from the calculation or defintion of the capacitances?

The user-manual describes the capacitance matrix as the imaginary part of the admittance matrix divided by the circular frequency (nu being the excitation frequency): \$Y=A+i2\pi\nu C\$
The admittance matrix is calculated by dividing the small signal current excitation vector with the small signal voltage excitation vector: \$\delta I=Y\delta V\$
If that's the case is it even possible to attribute a specific location to the calculated capacitances? Like this for all capacitances connected with the gate?:

schematic

simulate this circuit – Schematic created using CircuitLab

And maybe a negative current or a negative voltage explains why an admittance would be negative, but can this relation be transferred to the capacitance as well, which as the imaginary part can be negative for other reasons? There was already questions asked, why the capacitance is negative. In the answer, that \$C_{ij}\$ is \$C_{ij}\$ if \$i=j\$ and \$-C_{ij}\$ if \$i\neq j\$ (reference1), makes sense at first sight, but analysing a standard NMOS in TCAD (project: getting started/AC) at \$0.01Hz\$ shows, that \$C(s,d)=C(d,s) > 0\$, which would make sense if the capacitance itself is really negative (reference2). But negative capacitances seem only to show in transistors with ferroelectric materials, which is not the case for this NMOS.

Or is it like in Tsividis, Yannis (1999) on page 442 where this is written:

It will be helpful in this discussion not to associate the various capacitance parameters above with any physical capacitor-like structures in the MOS transistor.

I'm thankful for any input and I belive this can be an important discussion also for other people.

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Where does the capacitance lie? Can you think about the capacitance like a plate capacitor sitting between the terminals? If yes, what capacitance is C(g,g) describing?

Capacitance can happen (or be modeled, remember capacitors are just a model of the physical world) between two conductors. Also the material between the two can change the permittivity, so it must also be taken into consideration.

You can use the parallel plates model but the capacitance in a fet could be modeled more accurately by also representing fringing fields.

At that point you could pull out a 3D FEM or use 2D methods and electromagnetic field theory

enter image description here Source: https://www.semanticscholar.org/paper/Fringe-capacitance-model-of-a-double-gate-MOSFET-Kosala-Nandi/37e9014d628c31799648e1050b4d6e82dc339897

Why are capacitances negative? Does it mean that the capacitance is really negative, or does this phenomena arise from the calculation or defintion of the capacitances?

It has more to do with dielectrics and semiconductors, it also could have something to do with their model and what makes sense for it.

If that's the case is it even possible to attribute a specific location to the calculated capacitances? Like this for all capacitances connected with the gate?

No, remember capacitors and circuits are just ways for us to simplify and model circuits and their effects.

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  • \$\begingroup\$ First I want to thank you for answering my question. It gave me a new perspective. \$\endgroup\$
    – zraibra
    Oct 28, 2022 at 11:37
  • \$\begingroup\$ It makes perfect sense to me that the capacitance lies between two electrodes like with C(g,s), even if they are not parallel to each other, but this leaves me headscratching when looking at C(g,g), what would you suggest are the two electrodes in this case? Also I want to add, that in the reference you gave regarding the negative capacitance, the author also mentions ferroelectric material in which this phenomenon occurs. But when I simulate a NMOS there are also negative capacitances without the ferroelectric material. So I am unsure about the material being the reason for it. \$\endgroup\$
    – zraibra
    Oct 28, 2022 at 11:44
  • \$\begingroup\$ I'd imagine that C(g,g) would be the capacitance from the metal wire to the lower part of the gate. Also this: meta.stackexchange.com/questions/126180/… \$\endgroup\$
    – Voltage Spike
    Oct 28, 2022 at 15:56
  • \$\begingroup\$ Wouldn't C(g,g) in that case need to use the voltage and current between metal wire and lower part of the gate? \$\endgroup\$
    – zraibra
    Oct 31, 2022 at 12:43

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