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In 1976, the Z80 processor ran at 2.5 MHz and a typical DRAM access time was 500 ns. Now, processors run at 4 GHz and DRAM access time is 50 ns. Thus, processors are over three orders of magnitude faster but DRAM accesses are only one order of magnitude faster.

What are the technical reasons for this?

Why doesn't scaling help DRAM the same way it helps CPUs?

My hypothesis is that manufacturers increase DRAM capacity as transistors shrink, so the bit lines remain about the same length. Thus, the bit line capacitance doesn't scale down much and R-C delays on the bit lines keep DRAMs slow. Would a 1970s-sized 1-kilobit DRAM keep up with CPU speeds with modern technology, or are there other limiting factors?

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    \$\begingroup\$ I don't know the answer, but maybe L1 cache - which nowadays has an access time on the order of 1 ns - would make a fairer comparison. Caches are far more critical nowadays than they were in the 70s. \$\endgroup\$
    – TypeIA
    Oct 25, 2022 at 17:56
  • \$\begingroup\$ Maybe @TypeIA is on the right path. DRAM is external to the chip, and thus has lots of capacitance to contend with vs internal on die memory. \$\endgroup\$
    – Aaron
    Oct 25, 2022 at 18:19
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    \$\begingroup\$ DRAM is a relatively slow type of memory to begin with. It trades cost for speed. \$\endgroup\$
    – user253751
    Oct 25, 2022 at 18:49
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    \$\begingroup\$ @TypeIA While caches are an interesting topic, for this question I'm specifically interested in dynamic RAM. \$\endgroup\$
    – Ken Shirriff
    Oct 25, 2022 at 19:19
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    \$\begingroup\$ Because cache. It's more important to improve the density of DRAM than to improve its speed. And density has improved about 5 orders of magnitude ... maybe nearer 6. \$\endgroup\$
    – user16324
    Oct 25, 2022 at 21:05

1 Answer 1

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One problem is the DRAM is located far away from the CPU, and the bus speed determines the bandwidth of data that the chip can handle.

The bus speed is determined by PCB design and layout and not chip design, things like trace/net timing and termination affect the clock speed of the memory and not the chip itself. Trace width and length, The PCB dielectric constant, PCB thickness, copper weight all determine how fast the clock speed of the memory. This has limits and is hard to achieve high speeds. The higher speed that is needed the more these constraints need to be controlled.

Maintaining clock speeds on the same chip is a bit easier because of the distance involve, it's much shorter and easier to maintain high speeds.

The other problem is the speed of accessing DRAM is done with amplifiers that must read a row/column and these can only operate so fast, so the refresh is limited by the size of the DRAM and the analog sense circuitry and the column and row addressing. That has improved but it does not scale like mores law does. You can see the improvements over time here

enter image description here
Source: https://slideplayer.com/slide/4139713/

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    \$\begingroup\$ Thank you for the detailed answer. A 3 GHz DRAM bus would add under a nanosecond of delay, however, so I don't think the bus explains why an access takes 50 ns. \$\endgroup\$
    – Ken Shirriff
    Oct 25, 2022 at 19:21
  • \$\begingroup\$ Forgot about that part. \$\endgroup\$
    – Voltage Spike ♦
    Oct 25, 2022 at 19:29
  • \$\begingroup\$ @KenShirriff: What 3GHz bus do you know of with 64 or more parallel data signals? \$\endgroup\$
    – Ben Voigt
    Oct 25, 2022 at 19:39
  • \$\begingroup\$ The access is due to the structure of the Column Address System, but that isn't what determines the bandwidth of the DRAM or how fast it runs, that is determined by the PCB. CAS runs a few clocks slower than the main clock \$\endgroup\$
    – Voltage Spike ♦
    Oct 25, 2022 at 19:55
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    \$\begingroup\$ @KenShirriff: The DRAM clock speed (or oversampling I/O speed) determines burst throughput.... transfer time between successive words moving in the same direction. That is indeed down near 1ns, and can be less than the round-trip delay through I/O buffers and synchronizers. The access time you asked about in your question, is to setup access to an arbitrary address, sent from memory controller to DRAM, and then do an access. That requires bidirectional data flow. \$\endgroup\$
    – Ben Voigt
    Oct 25, 2022 at 20:51

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