For ambiguous state, both outputs x and y must be zero(for active low) to be considered invalid i.e. of both PRESET and CLR are logic "0". Now, analysing the circuit, $$ x=a \oplus D_0 $$ and $$ y= D_2 \oplus MSB $$ that means either
$$a=D_0=0 \\ or \\ a=D_0=1 $$ and $$ D_2=MSB=0 \\ or \\ D_2=MSB=1 $$
if $$a=0, b=0, and \ c=1$$ then LSB = 0 and MSB = 1 implies $$D_1 = 1$$ and $$D_0,D_2,D_3=0$$ but since $$MSB = 1$$ output of XOR gate will give Y=1.
Why is the correct answer a=0,b=0,c=1 ?