Getting the warning WARNING:Xst:1710 and WARNING:Xst:1895 while running my top module

Question

My aim is to find the pulse width of an unknown incoming signal. To that I have written the following synthesizable verilog code but I am getting the warning XST 1710 and XST 1895. When I try to simulate the code, I get 'XXXXXX' in red.

Top module:

`timescale 1ns / 1ps

    module top( input clk_100mhz,
                    input inp,
                    input reset,
                    output [13:0] average
        );
    
    wire [13:0] w_width;
    wire [13:0] w_sum;
    
    pulse_counter pc(.clk_100mhz(clk_100mhz),
                          .inp(inp),
                          .reset(reset),
                          .width(w_width));
                          
    adder a(.width(w_width),
              .sum(w_sum));
              
    averager avg(.clk_100mhz(clk_100mhz),
                     .reset(reset),
                     .sum(w_sum),
                     .average(average));
    
    endmodule

Pulse Counter Module:

module pulse_counter(   input clk_100mhz,
                        input inp,
                        input reset,
                        output reg [13:0] width
    );
reg [13:0] counter;


always @(posedge clk_100mhz or posedge reset)

if (reset) begin
counter <= 14'd0;
end

else begin
    if(inp == 1) begin
    counter <= counter + 14'd1;
    end
   if(inp == 0) begin
        width <= counter;
        counter <= 14'd0;
    end



end
endmodule

Adder Module:

`timescale 1ns / 1ps

module adder( input [13:0] width,
                output reg [13:0] sum = 14'd0
    );

always @(width) begin
sum = sum + width;
end


endmodule

Averager module:

`timescale 1ns / 1ps

module averager( input clk_100mhz,
                      input [13:0] sum,
                      input reset,
                      output reg [13:0] average
    );
reg [27:0] counter;

always@(posedge clk_100mhz or posedge reset) begin
if (reset) begin
counter <= 28'd0;
end

else begin
counter <= counter + 28'd1;
    if (counter == 100000000) begin
    average = (sum + 14'd50) / 14'd100;
    counter <= 28'd0;
    end
end

end
endmodule

Warning:

WARNING:Xst:1710 - FF/Latch <avg/average_8> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <avg/average_9> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <avg/average_10> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <avg/average_11> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <avg/average_12> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <avg/average_13> (without init value) has a constant value of 0 in block <top>. This FF/Latch will be trimmed during the optimization process.

Simulation Output:

Test Bench:

`timescale 1ns / 1ps

module toptb;

    // Inputs
    reg clk_100mhz;
    reg inp;
    reg reset;

    // Outputs
    wire [13:0] average;

    // Instantiate the Unit Under Test (UUT)
    top uut (
        .clk_100mhz(clk_100mhz), 
        .inp(inp), 
        .reset(reset), 
        .average(average)
    );

    initial begin
        // Initialize Inputs
        clk_100mhz = 0;
        inp = 0;
        reset = 0;
#10 reset = 1;
#10 reset = 0; 
        // Wait 100 ns for global reset to finish
        #100;
        
        // Add stimulus here

    end
  always #5 clk_100mhz = ~clk_100mhz;
always #10000 inp = ~inp;  
endmodule

I have been stuck here for sometime now and I couldn't solve the issue. Would really be helpful if someone helped me in solving this issue.

Answer 1

In module averager, you declare average as a reg type. The means it is initialized to X at time 0. The 1st time you assign another value to it is when counter is 100000000. You need to wait 100 million clock cycles before that happens, but your waveforms only show about 50 cycles.

You need to run your simulation for much longer. Or, if you don't like the red X's in your waves, you should reset the signal, just as you reset the counter:

always @(posedge clk_100mhz or posedge reset) begin
    if (reset) begin
        counter <= 28'd0;
        average <= 0;
    end

Regarding the warnings, I suspect your tools are referring to the divide by 100 code:

average = (sum + 14'd50) / 14'd100;

100 requires 7 bits. I think the tool might be telling you that the 7 LSB's of average are not needed.