Performance metrics for a VHDL/Verilog RTL design

Question

Correctness and performance is everything in programming. Verifying it for software is relatively easy because you can "just" run the program and see if it crashes and/or is very slow. Verifying correctness for hardware is also relatively easy because you can run the design in a simulator, but verifying performance (gate count, f_max, energy usage, size in um^2, etc.) is tricky.

So my question is how you do it when you don't have access to the target hardware (e.g ASIC or high-end FPGA)? What free tools are there that can give you (approximate?) performance metrics for HDL designs?

Answer 1

The vendor FPGA toolchains will do fairly exact performance analysis, giving the exact resource counts, f_max for each clock, energy usage and required cooling solution, all during compilation.

Timing analysis is partially required for synthesis anyway, to decide optimum placement, and once synthesis is complete, a separate verification pass is performed. It is entirely possible that timings and energy usage for different synthesis attempts vary quite a bit.