As we know, the waveforms of the I2C signals (SDA and SCL) are very similar to the following:

enter image description here

The main requirement is that during the transmission of a byte, the SDA does not transition while SCL is high. In fact, in that case a STOP condition arises 2. The SCL is driven by the master so how can the slave asynchronously drive the SDA? Does it have an internal PLL to produce a faster internal clock (I am thinking a clock frequency twice the SDA frequency), or can the slave just switch SDA at the falling edge of SCL?

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    \$\begingroup\$ That's not a very well drawn diagram. In my experience the I2C slave will assert ACK on SDA on or immediately following the SCL falling edge after D0. \$\endgroup\$
    – brhans
    Oct 28, 2022 at 16:39
  • \$\begingroup\$ I can do nothing but agree. But please, still consider my question since the byte transmission wafeform is correct and my question is about it and how the slave manages to generated that wafeform. \$\endgroup\$
    – acefrrag
    Oct 28, 2022 at 16:54
  • \$\begingroup\$ My point is that the byte transmission waveform in the image in your question is not correct. The SDA transitions should line up with the SCL falling edges for anything other than the Start or Stop conditions. A real I2C transaction does not look the that shown in your image - ACK is asserted by the slave when the master drives SCL low after the last data bit, and does not change while SCL is high. \$\endgroup\$
    – brhans
    Oct 28, 2022 at 17:06
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    \$\begingroup\$ I don't follow the question. When reading from slave, SDA out from slave is always updated when falling edge of SCL has happened. So it's synchronous to SCL. If the slave is an MCU it can react after falling edge and set a byte for transmission. It is possible to see that kind of glitch but an MCU as a slave can stretch clock. But likely that's just a bad diagram. Refer to I2C specification. Let me know if I should expand some detail and convert this into answer. \$\endgroup\$
    – Justme
    Oct 28, 2022 at 17:09
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    \$\begingroup\$ As soon as the slave sees the falling edge of SCL it can pull down SDA. Not sure why this would be confusing. \$\endgroup\$
    – user253751
    Oct 28, 2022 at 17:56

1 Answer 1


Many I2C slave devices (microcontrollers, for example) will have an internal clock that runs continuously and at a much higher rate than the I2C clock. These devices will simply drive SDA on an internal clock edge that happens some time after they observe SCL to be low.

Simple I2C slaves (certain ADCs, bus switches, etc) will use the SCL falling edge to time their SDA transitions. Simple causality and gate delays will ensure the SDA transition occurs at least a few nanoseconds after SCL has fallen. The known maximum clock rate for the I2C protocol being used will allow the designer to ensure the SDA transition happens before the next rising edge of SCL.

For lower speed I2C protocol (100 kHz for sure, maybe also for 400 kHz but I don't remember for sure) devices that are very slow can also hold SCL low themselves to give themselves time to update SDA before SCL is allowed to go high again. This is called "clock stretching".


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