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I was reading this paper about the Comparison of Adder Topologies, when I came across a page talking about the Carry Save Adder. They say on page 3:

The propagation delay is 3 gates regardless of the number of bits

They provide this schematic :

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As is clearly shown in the schematic, they are using a ripple carry adder in the lower half of the schematic, so how come "The propagation delay is 3 gates regardless of the number of bits" and at the same time, the propagation delay of a ripple carry adder is O(n)?

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The application and purpose of a carry save adder is to pay the price of carry propagation only once even when adding multiple numbers together. Such an adder is of no benefit when adding only two numbers.

For example, in a simple 8x8 bit multiplier, you'll need to add eight partial products together to form the 16 bit result. With a carry-save adder, the cost of carry propagation is distributed among the adder stages, so each stage propagates the carry only one bit to the left, and there are no long carry chains nor carry lookahead needed.

The carry-saved form can also be stored in an accumulator - a so-called carry-save accumulator. When you're adding multiple numbers to an accumulator but only need the final result, you can split the carry propagation among the partial sums. This can be of benefit when many wide additions are performed repeatedly into an accumulator - the carry-save adder takes a small amount of logic compared to a full adder with partial carry lookahead, and can be made extremely fast, even in gate-level implementations - by using multiplexers/pass gates.

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