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I'm currently designing an LLC resonant DC/DC converter with 12V input, +/-15V output and nominal 200W combined output power. I've already got my resonant circuit, transformer, gain curves and power stages working and optimized.

Right now I'm designing the converter's feedback loop. I'd like to use Bang-Bang charge control to turn the converter into a first-order lowpass, as that makes compensation really easy.

Here's my circuit (please excuse the huge image): Simulated LLC converter

LTSpice ASC file (Github Gist)

The problem I'm having is that the circuit works absolutely perfectly, but I don't quite understand why. Specifically, I just don't see the negative feedback mechanism that keeps the duty cycle at 50% (and, therefore, the DC offset across the resonant tank circuit at zero).

To check if there really is a feedback mechanism (and I haven't just gotten lucky in the simulation), I added a voltage source Vdc_error in series with the resonant tank circuit. This voltage source is initially zero and adds a huge DC voltage offset at t=3ms (red trace in the simulation plot). As can be seen from the green trace (PWM waveform), the duty cycle initially deviates from 50% once the offset has been added but returns to 50% just one cycle later, which means that there really is a strong negative feedback pushing the duty cycle towards 50%. (This, in turn, then also compensates the DC offset by putting -5V onto Cres to cancel out the 5V from Vdc_error.)

Unfortunately, I just know that the negative feedback exists (and that's a good thing), but I'd also like to know how this negative feedback happens. The only feedback path in this circuit is via transformer L6/L7/L8, which I use to measure the resonant capacitor voltage to implement the aforementioned Bang-Bang charge control scheme. However, since this is a transformer, the feedback signal is AC-coupled, which means that it simply can't see the DC offset voltage on Cres. Yet the circuit is still able to perfectly compensate for DC offset in the resonant tank circuit somehow. Even adding a voltage ramp in series with Cres doesn't trip it up; the overall offset voltage stays exactly at zero.

TL;DR: Where's the negative feedback path in this circuit that keeps the duty cycle at 50% and DC offset at zero, and how does it work? I might just be blind, but I can't see it.

Edit: This is what the capsense transformer feedback voltage looks like when the Vdc_error voltage gets applied. It's quite easy to see that it becomes asymmetric at that moment in time. The capsense transformer is good enough to reproduce the asymmetric waveform accurately during the time it takes the converter to restore 50% duty cycle again, so it's not the capsense transformer itself that forces symmetry. (The DC current that the asymmetric feedback signal causes in the transformer's primary also doesn't reach a value that's high enough to make it saturate. Its frequency response is flat down to low enough frequencies to reproduce it, too.)

Capsense transformer output voltage when the DC error is applied

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  • \$\begingroup\$ What are V5 and V6 doing? \$\endgroup\$
    – Andy aka
    Commented Oct 29, 2022 at 16:51
  • \$\begingroup\$ V5 and V6 are the load of the converter. LLC resonant converters with bang-bang charge control produce a constant output current, rather than an output voltage, so the ideal test load is a voltage source. The current setpoint is determined by V1 (which can be varied from 100mV to 4V; the output current follows linearly). \$\endgroup\$ Commented Oct 29, 2022 at 16:53
  • \$\begingroup\$ Doesn't CAPSENSEA and B feedback ensure 50% duty \$\endgroup\$
    – Andy aka
    Commented Oct 29, 2022 at 16:57
  • \$\begingroup\$ Well, that's the problem - I'm not sure about that. An asymmetric PWM duty cycle would induce an asymmetric voltage across Cres, which in turn would cause asymmetric feedback via the capsense transformer... (Zero DC, but different waveform shape during the positive/negative phase.) And that creates asymmetric PWM again. I'm starting to think that the sinusoidal resonant waveform that is superimposed on the potentially asymmetric Cres voltage nudges things towards 50% duty cycle and symmetry, but I'm still not totally sure. \$\endgroup\$ Commented Oct 29, 2022 at 17:02
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    \$\begingroup\$ I suspect the bang-bang charge-control as implemented by recent integrated circuits does not naturally include a 50% duty ratio symmetrization and I think the real embodiment adds this function, at least for the start-up sequence. I built a small-signal model in SIMPLIS and the ac response is really stable across line and load conditions. You can have a look at my new seminar on LLC control methods. \$\endgroup\$ Commented Oct 30, 2022 at 8:08

3 Answers 3

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The Vdc_error, R11 || C10, Cres combination -- assuming R11 is large enough to ignore (dampening for the coupling cap C10?), means the error is absorbed in the capacitors as DC voltage drop.

Notice the duty cycle trends back to 50% after the transient. If C10 and the CAPSENSE path were DC coupled (you could use a diffamp for this), feedback would be DC coupled and it should continue at the new duty cycle.

Somewhat unrelated: if this is just for testing, no problems. But full bridge and LLC are unusual choices at such low voltages, and especially if you're going to ramp up to the kind of currents AOB2144L can deliver, it's difficult/impossible to find capacitors large enough (in C and Irms) at low voltages to do that kind of thing. A push-pull forward converter is generally the best choice for that range. At that, I would recommend keeping currents under say 50A peak or so, maybe even less, and use multiple converters in parallel to reach the desired total -- their clocks can be phase-shifted to reduce input and output ripple current, saving some on capacitor size.

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  • \$\begingroup\$ Yeah, R11 is just to dampen C10/L9 as they'd otherwise resonate. I'm slowly coming to believe that the large sinusoidal resonant waveform that's superimposed onto any potentially asymmetric PWM signal prevents asymmetry from building up, thereby preventing "duty cycle drift", which is the thing I'm worried about. Does that make sense to you? About the unusual choice of topology: I'd need two forward converters for tightly regulated +/-15V, while I only need one LLC to do the same thing. EMI is lower with LLC too and I already found capacitors that can handle the Irms (25A). \$\endgroup\$ Commented Oct 29, 2022 at 22:15
  • \$\begingroup\$ @JonathanS. Try it with VCVS or ideal transformer instead of coupled inductors -- it's a simulation after all, can take liberties like that. It looks to me, a simple matter of superposition, and the load and feedback are AC coupled so the DC component simply disappears. With DC coupled feedback, you should see the duty shift persist. All the resonant tank cares about is the fundamental, which will change only modestly for small shifts in duty (~sin(pi*duty)). \$\endgroup\$ Commented Oct 29, 2022 at 23:58
  • \$\begingroup\$ It's clear to me that I will get duty shift with DC coupling. The real issue that I have is this: Why doesn't the duty cycle drift away from 50% on its own, without external perturbation? I only inserted the DC error voltage source to check if any kind of strong negative feedback is present that steers the duty cycle back to 50%. That is obviously the case, but where does this negative feedback come from? After all, asymmetric PWM -> asymmetric current waveform -> asymmetric Cres waveform -> more asymmetric PWM. But the loop gain seems to be smaller than 1, steering it back to 50%. Why? \$\endgroup\$ Commented Oct 30, 2022 at 0:16
  • \$\begingroup\$ @JonathanS. Clearly the converse is true: no DC coupling, no duty error. The circuit is symmetric and I don't see any obvious symmetry-breaking, so that simply seems to be it. Perhaps you'll find if the transformer or inverter, as-built, has weird strays in it, which break symmetry? As a general feel, I don't like edge triggered oscillators like this: besides unpredictable behavior, if for any reason it misses an edge, it freezes up, and, that's just game over; lights on, nobody's home, gotta power cycle it, or maybe kick it with a watchdog or some other hack. \$\endgroup\$ Commented Oct 30, 2022 at 2:04
  • \$\begingroup\$ (And by "unpredictable", I mean behavior that either depends on things you might not be aware of, like strays, or behavior that doesn't seem to have a reason to show up yet does (symmetry breaking, limit cycle), or more specifically, that you can't prove it won't do something unexpected, whereas a more canonical (e.g. VCO + PLL) form is easy to prove the behavior of.) \$\endgroup\$ Commented Oct 30, 2022 at 2:06
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Given the structure of the bang-bang controller, as you implemented this (the subcircuit with U1, U2, A1-A4 etc.), the duty cycle in the steady state cannot be anything other than 50%. As you notice, since L6/L7/L8 is a transformer, the feedback signal is AC-coupled. The passive subcircuit R15/R13/L7/L8 is symmetric, and the voltages at the two nodes CAPSENSEA and CAPSENSEB are waveforms vertically flipped with respect to each other because of the opposite L7/L8 winding directions.

CAPSENSEs

These voltages are rectified by diode pairs D5/D15 and D14/D16, the rectified values are compared with a FIXED_ISET voltage, and, in the steady state of the controller operation, finally give identical logic signals at the U1/U2 outputs shifted by a half period.

ISET_1V

I took a liberty to move the ENABLE signal start to 0.001ms and the error voltage (Vdc_error) start to 0.1ms for the convenience of watching the waveform plot.

The insensitivity of the duty cycle with respect to DC component variations can be also demonstrated with changing the FIXED_ISET parameter (reference voltage at the comparators U1/U2)

ISET_100mV

FIXED_ISET = 100mV

ISET_1.8V

FIXED_ISET = 1.8V

Of course, the duty cycle is gradually changing while the output current is tending to its steady state value, this value is set by a FIXED_ISET voltage.

The plot of steady state waveforms

STEADY

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The bang-bang charge control technique for the LLC converter has been introduced by the Queen's university in Kingston (Canada) and this paper from Yan-Fei Liu's team documents the operating principle. Rather than directly controlling the switching frequency (direct frequency control, DFT), the regulating block sets the peak and valley voltages on the resonating capacitor, effectively adjusting the energy stored and released cycle-by-cycle. The switching frequency is indirectly controlled - like peak current-mode control which indirectly sets the duty ratio - and offers a very friendly control-to-output transfer function, easy to compensate.

The below figure shows a possible implementation of the modulator section which symmetrically adjusts the peak and valley voltages of the resonant capacitor based on an error voltage. One possible drawback of this approach is the lack of exact 50% duty ratio on the high-voltage node which could generate current imbalance in the transformer windings. I think integrated circuits include a correcting circuitry to make sure the duty ratio is kept constant during transient events (load steps and start-up) but this simplified model does not.

enter image description here

It is then possible to build a subcircuit which includes a simplified control mechanism, enough to obtain the ac response of the circuit. This is what I've done for my last seminar dedicated to control techniques for LLC converters available here and you can download the circuit which operates on the free demo of SIMPLIS from my webpage.

enter image description here

From this circuit, you immediately obtain the operating point as illustrated below and can see how the duty ratio nicely establishes to 50%:

enter image description here

But the most useful information which is delivered by SIMPLIS remains the ac response obtained in a few seconds from this switching circuit:

enter image description here

As you can see, the gain is almost insensitive to the input voltage and the response is that of a 1st-order circuit. Once compensated in the right side, phase margin and crossover are almost constant, regardless of the output current, something impossible to obtain with direct frequency control.

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