Is it possible to write the following code using a for
loop in Verilog?
i = 0: sum[0] <= data[0];
i = 1: sum[1] <= data[0] + data[1];
i = 2: sum[2] <= data[0] + data[1] + data[2];
i = 3: sum[3] <= data[0] + data[1] + data[2] + data[3];
.
.
i = 7: sum[7] <= data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];