# Confusion with edge-triggered D-type flip-flop in code by Charles Petzold

I am confused about a circuit which is presented in Charles' Petzold's 'Code' book (Page 178), and I would like some clarification. The book says that the following flip-flop is edge-triggered:

I don't think this is the case unless I'm really stupid, but I hope that isn't the case.

The book does provide, earlier in the book, an example which I fully understand (Page 171):

In the example I am confused about it seems that it is level-triggered because after Clock is set to 1, Data still holds the ability to change the value of Q, as Clock does not control the flow of Data when it is both on and off; only when it is off does it prevent Data from making an impact, making it level-triggered, I believe.

The correct example I show only lets Data have an impact when Clock goes to 1, as there are two layers, and when Data flows to Q, Clock must be set to 0 in order for the data that will be sent to the second layer to be set, so I do understand that.

The two flip-flops, I am certain in saying, are inherently different due to the difference in the number of layers, and if an edge-triggered flip-flop can be made with one layer, why hasn't it been presented as an example instead?

Basically, am I right in this? I would like clarification from somebody who may understand it better. Is the book correct?

• The first diagram is indeed an edge-triggered flip-flop, but its operation is far from obvious. But it's the exact same diagram you'll find in any datasheet for a 74xx74 dual DFF, for example. Analyzing ASMs (asynchronous state machines) at this level requires a great deal of patience and attention to detail. It may be helpful to eliminate the Preset and Clear inputs and analyze the resulting simplified logic. Oct 31, 2022 at 0:24
• Ok, thanks for the suggestion. Oct 31, 2022 at 9:32

Q  Qn  CLK  X  Y  Z  W