NOR Flash endurance: damage happens during Program or Erase?

Question

In NOR Flash memories, the endurance of the device is generally measured in (P/E) cycles. This datasheet is a typical example.

My question is, in a P/E cycle, when does the damage occur? If I perform repeated erase operations without interleaved program operations, does that eat up my endurance? How about repeated 'P's without interleaving 'E's?

My vague understanding from reading the wiki article is that both Programs and Erases involve applying high voltages to some of the terminals of the floating gate mosfet, but only programming involves high currents and "hot carrier injection". No idea if this means something though.

Answer 1

TI's MSP430 Flash Memory Characteristics application report says:

3.2 Flash Endurance
[…] The most common problem is stuck cells caused by charge trapping. Charge trapping occurs in the insulating tunnel oxide during erase operations, causing the cell to read a logic 0 although erased. This is a self-healing effect and usually detraps automatically in the quiescent period after an erase cycle. During endurance testing at Texas Instruments, the flash cells are continuously erased and rewritten. With a delay of at least one or two seconds between two erase and write cycles, the flash endurance increases significantly during the tests.
[…]
3.3 Cumulative Program Time
[…] Writing to the same row too many times can result in write disturb, and erased bits will be programmed as well. This produces no physical damage and, after erase, the disturbed bits are programmable as before. No long term effects are known.

So erasing is worse.

(Other NOR flashes should behave in the same way.)