# How can I bias my output voltage after op-amp?

I am trying to build a circuit using a CA3140 to amplify a small voltage and output 0~3.3 V, like below (please ignore R4, I was debugging another signal source): By running a simulation, I get my Vout and V(TO ADC) like: But I expected something like: Referring to Opamp: amplifying DC bias problem in output? I tried to connect pin 4 to GND directly but I lose all negative signals like: If I don't want an offset at the input side, is there any way to offset at the output?

• Is R4 dangling in the air? Nov 2, 2022 at 11:25
• Yes, R4 is now usless, I was debuging with another signal source Nov 2, 2022 at 12:04

I'm not sure why you need to distinguish between biasing on the input side, and biasing at the output, but I'll assume it's because you don't want to have any AC coupling capacitor at the input, or any bias resistances that might load the source signal.

Ironically, capacitor C1 is introducing a bias at the input side, but since you seem to be OK with that, I'll also assume that you will be happy with any input tweaks to the op-amps input that don't mess with the original input signal in any way.

Things get a lot easier if you can write the relationship you require between input and output potentials algebraically. This requires you to state explicitly what input potential maps to what output potential. If I understand your circuit correctly, you're looking for a gain of 3.3, with an output that swings between a maximum of +3.3V and minimum 0V. I'll also assume (from your graph) that the input signal is centered on 0V, and (if I'm right about the gain) should therefore swing between +0.5V and −0.5V.

Usually we'd start the design process with input range and corresponding output range. I'll pretend that's what we're doing here. Start by calculating required gain, which is easy enough; it's the ratio between full output swing and full input swing:

\begin{aligned} A &= \frac{+3.3 - 0}{+0.5 - (-0.5)} \\ \\ &= \frac{3.3}{1} \\ \\ &= 3.3 \end{aligned}

Now figure out what offset (output bias) you require. That's just a question of finding the output you expect when the input is zero. It's trivial in your case, since zero input should correspond to the midpoint of the output range:

\begin{aligned} V_{OFS} &= \frac{(+3.3) - (0)}{2} \\ \\ &= 1.65 \end{aligned}

Now we can build an equation relating output to input:

\begin{aligned} V_{OUT} &= A \times V_{IN} + V_{OFS} \\ \\ &= 3.3 \times V_{IN} + 1.65 \end{aligned}

A quick check will show you that $$\V_{IN}=-0.5 \rightarrow V_{OUT}=0\$$ and $$\V_{IN}=+0.5 \rightarrow V_{OUT}=+3.3\$$

Now we have an algebraic representation of that relationship, we can build a generic op-amp circuit to implement it. Here's a starting point: simulate this circuit – Schematic created using CircuitLab

I'll choose R1 arbitrarily, to be 10kΩ. Since we require a gain of 3.3, we can use the well known gain formula for this non-inverting configuration to calculate R2:

\begin{aligned} A &= 1 + \frac{R_1}{R_2} \\ \\ R_2 &= \frac{R_1}{A - 1} \\ \\ &= \frac{10k}{3.3 - 1} \\ \\ &= \frac{10k}{2.3} \\ \\ &= 4.3k \end{aligned}

Now we find the potential required at B, $$\V_B\$$. This will introduce the bias required at the output. With negative feedback, an op-amp will adjust its output to whatever value causes its inverting and non-inverting inputs to have the same potential. In other words, $$\V_Q = V_{IN}\$$. We have a potential divider formed by R1 and R2, which will present a potential at Q which is a function of $$\V_{OUT}\$$, $$\V_B\$$, R1 and R2 as follows:

$$V_Q = V_{IN} = (V_{OUT} - V_B) \times \frac{R_2}{R_1+R_2} + V_B$$

We already have input-to-output potential mappings for several values of $$\V_{IN}\$$ and $$\V_{OUT}\$$, any of which we may plug into this equation to solve for $$\V_B\$$, but I suspect the easiest values to solve for are when $$\V_{IN}=0\$$. Zeros almost always simplify things, and we know that in that condition our output should be $$\V_{OUT}=1.65\$$. Let's plug those values in and solve for $$\V_B\$$:

\begin{aligned} 0 &= (1.65 - V_B) \times \frac{4.3k}{4.3k + 10k} + V_B \\ \\ &= (1.65 - V_B) \times 0.3 + V_B \\ \\ &= (1.65 \times 0.3) - V_B \times 0.3 + V_B \\ \\ &= 0.5 + V_B(1 - 0.3) \\ \\ V_B &= \frac{-0.5}{0.7} \\ \\ &= -0.71 \end{aligned}

This circuit will work fine to implement the input/output equation we started with, but it requires a voltage source of −0.71V. You can use any method you like to generate that, but its source impedance must be very small compared to R1 and R2, to avoid upsetting the carefully engineered gain of 3.3. Alternatively, if you trust your power supply to be stable and accurate, we can use a potential divider to replace R2, and derive −0.71V, ensuring that its Thevenin equivalent resistance is equal to R2: simulate this circuit

In other words, if the potential divider consists of resistors R3 and R4 between ground and −5V, for instance, two conditions must be met. Firstly, the voltage at their junction should be be −0.71V:

$$-5 \times \frac{R_3}{R_3 + R_4} = -0.71$$

Secondly, their Thevenin equivalent resistance, which is their combined resistance as if they were connected in parallel, should be 4.3kΩ:

$$\frac{1}{R_3} + \frac{1}{R_4} = \frac{1}{4.3k}$$

I won't write out the algebra here, but the solution to those two simultaneous equations is:

\begin{aligned} R_3 &= 5k\Omega \\ \\ R_4 &= 30k\Omega \end{aligned}

The resulting plot of $$\V_{OUT}\$$ vs $$\V_{IN}\$$ looks like this: In this circuit, the input signal is completely unloaded, since the op-amp has very high input resistance, and everything is DC coupled - not a capacitor in sight.

• It is really comprehensive, especially for software engineers like me, thank you! Nov 3, 2022 at 1:55

The dc offset of V(TOADC) is determined by the values of the two resistors at the output R6 (100k) and R8 (10k) and also by the value of the voltage supply attached to those resistors (PO55).

It looks to me that with V(TO ADC) centred on +0.45 V and the values of those two resistors that you are using a voltage of +5 V for PO55.

Now to centre V(TO ADC) half way between 0 V and +3.3 V with PO55 being equal to +5 V you just need to chose the correct values for resistors R6 and R8.

The approximate resistor ratio you need for R6:R8 is 2:1. So make R6 twice the value of R8.

Those two resistors form a high pass filter in conjunction with capacitor C2 and so R6 & R8 must be made high enough in value so as not to attenuate low frequencies. You don't actually say what frequency band is of interest to you but the current values for R6 & R8 should give a guide if they are suitably sized.

That op amp is probably unsuitable for use with a +5 V supply for your application because I would expect the output to saturate (limit) before it reaches your required maximum voltage of +3.3 V. So, if you want to use that op amp you will have to increase its positive supply voltage a little and if you do that you will have to calculate a new ratio for R6:R8 to re-centre the output waveform on +1.65 V.

Set the ADC input to 1.65 V by changing the 100 kΩ resistor to 20.3 kΩ. The output voltage of the amplifier should not be higher than 3.3 Vpp. C1 at your schematic (10 µF) is unnecessary, the gain is small, so the output DC (offset) voltage also remains small.  