MOSFET high frequency gate driving

Question

For a custom MCU driven boost converter I'm trying to drive a power MOSFET IRF520N at 700kHz.

In order to reduce RdsOn and switching losses I have added a logic MOSFET 2N7000 to drive the gate at 12V from a 3.3V PWM signal.

The power MOSFET gate is pulled up by a low value resistor in order to reduce transition time.

After looking at the power MOSFET gate with a scope, I saw that the PWM signal seems to be distorted. Worse than that is that there is only 6V left not 12V.

Could someone help me figure out why?

I know there are MOSFET drivers, and I plan to use it in a final design. My goal here is to perform a proof of concept with through hole components and veroboard.

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EDIT : i have also tested with a IRF44ZN instead of IRF520n , got more or less the same results, just less heat on IRF44ZN because of a better RDSon i think.

For now I added a 2n7000 as a pull resistor.

It seems better, Vgs now reach 12V however i have few questions because when i look at the MOSFET Drain (résistive load) i have a strange "response" when releasing the gate. Is this "normal" ? Sorry for be this naive but due to resitive loading i was expecting a perfect square wave but it seems that driving mosfet at this frequency is quite difficult...

Could someone explain what is this " Huge Voltage spike" when releasing gate ? (i hade to put my probe on x10 to measure it BTW)

I have tried to divide driving frequency by 2 it seems a little better because period is just longer does this means my MOSFET is too slow ?

VGS : MOSFET DRAIN 700Khz:

MOSFET DRAIN 350Khz:

Answer 1

If you haven't got a FET driver to hand, then you could bodge a faster pullup with an NPN like this

^{simulate this circuit – Schematic created using CircuitLab}

This radically reduces the capacitance that R1 has to drive high.

Answer 2

91 Ω pullup is too weak. You clearly see the slow turn-on with broad Miller plateau.

You have to reduce pull-up impedance using a push-pull gate driver.

Answer 3

IRF520N isn't a great MOSFET for switching a 12V load. If you can use a lower voltage FET, you will have many more FET options to choose from with lower RdsON for better conduction losses, lower gate charge for faster switching and lower switching losses, etc.

In addition if you want it to switch at 700kHz you will need very low inductance so a thru-hole MOSFET is again not an ideal choice. You will get much lower inductance with a flat SMD package and good routing, planes and decoupling caps very close by... It's one of these things that veroboard isn't really suited for. Even if it works, you won't be able to get meaningful measurements because wiring inductance will swamp everything.

From the scope shot it looks like it switches in 700ns which is totally incompatible with 700kHz switching.

You will need a fast FET driver with solid low inductance local decoupling, because when the driver turns the FET on, it dumps current from its own decoupling cap into the gate, so the inductance of the driver decoupling cap is in play.

The waveform looks normal: first gate voltage rises due to Cgs charging. Then there is the "Miller Plateau" where the FET turns on progressively and its drain voltage goes down from the supply voltage to zero. During this large change in Vds, the drain to gate capacitance absorbs all the gate current so Vgs stays constant, hence the flat waveform. Then once the FET is fully on, gate current again charges Cgs, raising Vgs until it reaches the maximum value from the driver.

Answer 4

As tobalt said, the Miller capacitance is the culprit. Always suspect it, the FET's capacitance between drain and gate, Crss. For fast switching, you must use a FET driver than can put out significant current, often several amps. That current charges and discharges Crss fast then steady state gate current kicks in, nA or uA.

Answer 5

"My goal here is to perform a proof of concept with through hole components and veroboard."

Been there, done that. Used a TC1411 driver, available in a DIP

Answer 6

Veroboard and hard-switching mosfets at 700kHz are mutually exclusive. If one is insistent enough, it usually ends up destroying the mosfet, and is an EMI nightmare.

For a proof of concept you would need:

• A much better gate driver - it can be discrete, just don’t think it only takes an NMOS and a pull-up resistor.
• A ground plane everything is mounted on - a thin brass or copper sheet, or a solid copper plane on laminate would both work
• Low parasitics packages - SMD everything, capacitors tombstoned on ground plane, connections made using wide copper strips to keep inductance low. 1206 packages will still be way better than anything with leads on a veroboard.

In a nutshell: you have to do everything you would do on a properly laid out PCB with SMD components, except without a PCB. It’s an interesting exercise but requires knowing what it takes to do a proper switcher PCB layout, then choosing not to lay out a PCB and do things manually as if making very miniature dollhouse decorations. The first few such contraptions take forever to get done, as with most things it gets easier with experience.

Start with the gate driver alone: you should be able to drive 12Vpp into a 1.5nF C0G/NPO SMT capacitor with <50ns rise and fall times. At least while getting there you will have a rather sturdy capacitor to drive - much more tolerant of abuse than mosfet gates.

The only way I see it easily done on veroboard is limiting gate slew rates to remain compatible with parasitics, and accepting the slow switching losses on the mosfet. And slowing down to 50kHz. It needs to be a scale model: higher parasitics implies slowing down, using a higher inductance inductor, etc. Proofs of concept don’t have to be 1:1 scale even in electronics! But scaling means not only mechanical dimensions but also speed (inversely), and everything that follows from that.

To get it going quickly, step-up the PWM to about 5-6V using an nmos and a pull-up (perhaps active pull-up), then use a 4000-series level translator to go to 12V, buffer with a 4041, then parallel a bunch of 4041s to drive the gate. 4000-series logic gets about as fast as is feasible on a veroboard. And use a mosfet designed for operation at the voltages you’ll be dealing with: they’ll have lower channel resistance and lower gate capacitance than the high voltage types.

I’ve got a bunch of 4041s and am quite interested in seeing how well it would work. Stay tuned :)

P.S. CD4041 is the fastest driver in the 4000 family, and a bit of an under-appreciated gem :)