We are driving a piezo transducer array with sub-1 μs pulses at an extremely low duty cycle. A single N-channel power MOSFET drives each transducer. Each power MOSFET transistor has a low side gate driver (FAN3229T) ahead of its gate to slew it quickly.
The transducer drive is not push-pull: there is no PMOS pull-up transistor to restore the transducer to its quiescent state. We have plenty of time between pulses so a simple resistor pull-up is fast enough to empty the transducer.
Here's another important piece of information: our 15 transducers all fire within 200 ns of each other.
I parked eight of these dual-port FAN3229T gate driver ICs next to the FPGA that creates the pulses. With no output load on the FAN3229Ts the FPGA is freaking out and resetting itself. The power MOSFETs and transducers are not present.
FPGA reset is caused by the eight FAN3229Ts boinking the ground plane they share with the FPGA. We can see these boinks with a fast scope. If we reprogram the FPGA to spread out its pulses in time (rather than all 16 be coincidental) the reset problem disappears.
Do unloaded gate driver ICs exhibit shoot-through current? The FAN series of gate driver ICs has a pair of push-pull MOS output transistors.
If there is indeed shoot-thru in the FAN gate drivers, I'm multiplying the shoot thru current by 16x when I ask all 16 FAN3229 channels to fire simultaneously.
Thanks in advance to anyone who can shed light on this.