Shoot-through inside gate driver ICs

Question

We are driving a piezo transducer array with sub-1 μs pulses at an extremely low duty cycle. A single N-channel power MOSFET drives each transducer. Each power MOSFET transistor has a low side gate driver (FAN3229T) ahead of its gate to slew it quickly.

The transducer drive is not push-pull: there is no PMOS pull-up transistor to restore the transducer to its quiescent state. We have plenty of time between pulses so a simple resistor pull-up is fast enough to empty the transducer.

Here's another important piece of information: our 15 transducers all fire within 200 ns of each other.

I parked eight of these dual-port FAN3229T gate driver ICs next to the FPGA that creates the pulses. With no output load on the FAN3229Ts the FPGA is freaking out and resetting itself. The power MOSFETs and transducers are not present.

FPGA reset is caused by the eight FAN3229Ts boinking the ground plane they share with the FPGA. We can see these boinks with a fast scope. If we reprogram the FPGA to spread out its pulses in time (rather than all 16 be coincidental) the reset problem disappears.

Do unloaded gate driver ICs exhibit shoot-through current? The FAN series of gate driver ICs has a pair of push-pull MOS output transistors.

If there is indeed shoot-thru in the FAN gate drivers, I'm multiplying the shoot thru current by 16x when I ask all 16 FAN3229 channels to fire simultaneously.

Thanks in advance to anyone who can shed light on this.

Answer 1

No, or generally not. But you might be seeing a similar effect.

Generally, drivers are designed to delay their two switches slightly, for obvious reasons. This goes from a convenience in small (200mA?) drivers, to required functionality in large (6A+) types!

There is still the capacitance of the output driver, where the PMOS is turned off, then NMOS turns on, and NMOS discharges its own capacitance (dissipated as power, no external current flow), and charges the PMOS's capacitance to VDD (dissipated as power, impulse current flows through supply bypass).

This capacitance is generally small (it's not rated, but may be inferred from the equivalent capacitance switching loss figure, which it will dominate), so it's not a good sign that it's causing problems already.

These current flows will only worsen once you add the MOSFETs, as their capacitance (and resistance, inductance and whatever other more complex characteristics may be relevant) add to supply and ground-return currents.

The solution in any case is better layout, particularly solid ground plane under each section (drivers and FPGA), with isolation of the currents flowing in the two sections (separate supply loop and return paths). This doesn't mean slotting a ground plane between them (for sure: do NOT route gate drive signals over a slot in the plane), but it can mean increasing the distance between them. Put the load on the far side, so that load current similarly flows in the local loop with the MOSFET, away from the driver. Place local bypass capacitors to source supply/load currents. If the FPGA is also supplied by the driver or load supply, consider an RC or LC filter to help isolate them, then regulate local to the FPGA.

Answer 2

Without knowing the detail or seeing a schematic, the problem is grounding. It isn't shoot through, that is when totem pole transistors are both on, effectively connecting the supply to the ground. Use split plane grounding. In other words, the FPGA and controller have a ground plane area and the piezo and driver has a ground plane area. These two planes are connected at a single point so that the power currents cannot affect the control area. Ignore the following, testing sub and superscripts: V_dd, 10^2.

Answer 3

The attached scope trace has 500mA per div vertical scale and 20 nsec per div horizontal.

The displayed signal is the shoot-through current viewed with a 1 ohm 0402 sense resistor placed in the VDD=+14V lead of a FAN3229T gate driver. Both channels of the FAN are connected together and triggered with the same pulse.

The measurement comes from a custom, postage stamp-sized PCB using nothing bigger than 0402s. The +VDD rail is rock solid. The PCB runs on a battery so it is floating with respect to scope ground.

The voltage across the 1 ohm sense resistor is measured with a U.FL coaxial connector with 4" of coax to the 'scope input.

My interpretation of the 'scope reading is that shoot-through current remains above 1 amp for at least 30 nsec and above 3 amps for a 10 nsec time window.

If I have qty=8 of these FANs running off the same FPGA clocking waveform, the array of gate drivers pounds on my FPGA's ground plane to the tune of ~10 amps.

This explains clearly why the FPGA is resetting.